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STM32F217VG 数据表(PDF) 25 Page - STMicroelectronics |
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STM32F217VG 数据表(HTML) 25 Page - STMicroelectronics |
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25 / 175 page  DocID17050 Rev 9 25/175 STM32F21xxx Functional overview 174 Figure 7. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization 1. This figure is valid both whatever the internal reset mode (ON or OFF). Figure 8. Startup in regulator OFF: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization 3.16.3 Regulator ON/OFF and internal reset ON/OFF availability VDD time 1.08 V PDR=1.8 V VCAP_1/VCAP_2 1.2 V time PA0 tied to NRST NRST VDD time 1.08 V PDR=1.8 V VCAP_1/VCAP_2 1.2 V time PA0 asserted externally NRST Table 3. Regulator ON/OFF and internal reset ON/OFF availability Package Regulator ON/internal reset ON Regulator ON/internal reset OFF Regulator OFF/internal reset ON LQFP64 LQFP100 LQFP144 LQFP176 Yes No No UFBGA176 Yes REGOFF set to VSS No Yes REGOFF set to VDD |
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