STM32F217VG datasheet(26/175 Pages) STMICROELECTRONICS

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Functional overview

STM32F21xxx

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3.17

Real-time clock (RTC), backup SRAM and backup registers

The backup domain of the STM32F21x devices includes:

•

The real-time clock (RTC)

•

4 Kbytes of backup SRAM

•

20 backup registers

The real-time clock (RTC) is an independent BCD timer/counter. Its main features are the

following:

•

Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date,

month, year, in BCD (binary-coded decimal) format.

•

Automatic correction for 28, 29 (leap year), 30, and 31 day of the month.

•

Programmable alarm and programmable periodic interrupts with wakeup from Stop and

Standby modes.

•

It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-

power RC oscillator or the high-speed external clock divided by 128. The internal low-

speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an

external 512 Hz output to compensate for any natural quartz deviation.

•

Two alarm registers are used to generate an alarm at a specific time and calendar

fields can be independently masked for alarm comparison. To generate a periodic

interrupt, a 16-bit programmable binary auto-reload downcounter with programmable

resolution is available and allows automatic wakeup and periodic alarms from every

120 µs to every 36 hours.

•

A 20-bit prescaler is used for the time base clock. It is by default configured to generate

a time base of 1 second from a clock at 32.768 kHz.

•

Reference clock detection: a more precise second source clock (50 or 60 Hz) can be

used to enhance the calendar precision.

The 4-Kbyte backup SRAM is an EEPROM-like area.It can be used to store data which

need to be retained in VBAT and standby mode.This memory area is disabled to minimize

power consumption (see Section 3.18: Low-power modes). It can be enabled by software.

The backup registers are 32-bit registers used to store 80 bytes of user application data

when VDD power is not present. Backup registers are not reset by a system, a power reset,

or when the device wakes up from the Standby mode (see Section 3.18: Low-power

modes).

Like backup SRAM, the RTC and backup registers are supplied through a switch that is

powered either from the VDD supply when present or the VBAT pin.

3.18

Low-power modes

The STM32F21x family supports three low-power modes to achieve the best compromise

between low power consumption, short startup time and available wakeup sources:

•

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

•

Stop mode

The Stop mode achieves the lowest power consumption while retaining the contents of

SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC

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