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STM32F217VG 数据表(PDF) 16 Page - STMicroelectronics |
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STM32F217VG 数据表(HTML) 16 Page - STMicroelectronics |
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16 / 175 page  Description STM32F21xxx 16/175 DocID17050 Rev 9 Figure 4. STM32F21x block diagram 1. The timers connected to APB2 are clocked from TIMxCLK up to 120 MHz, while the timers connected to APB1 are clocked from TIMxCLK up to 60 MHz. 2. The camera interface and Ethernet are available only in STM32F217xx devices. GPIO PORT A AHB/APB2 EXT IT. WKUP 140 AF PA[15:0] GPIO PORT B PB[15:0] TIM1 / PWM 4 compl. channels (TIM1_CH[1:4]N) 4 channels (TIM1_CH[1:4]), ETR, BKIN as AF TIM8 / PWM GPIO PORT C PC[15:0] USART 1 RX, TX, CK, CTS, RTS as AF GPIO PORT D PD[15:0] GPIO PORT E PE[15:0] GPIO PORT F PF[15:0] GPIO PORT G PG[15:0] SPI1 MOSI, MISO SCK, NSS as AF 8 analog inputs common to the 3 ADCs 8 analog inputs common to the ADC1 & 2 V DDREF_ADC 8 analog inputs to ADC3 4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR as AF 4 channels RX, TX, CK, USART2 RX, TX, CK USART3 RX, TX as AF UART4 RX, TX as AF UART5 MOSI/DOUT, MISO/DIN, SCK/CK SPI2/I2S2 NSS/WS, MCK as AF MOSI/DOUT, MISO/DIN, SCK/CK SPI3/I2S3 NSS/WS, MCK as AF SCL, SDA, SMBA as AF I2C1/SMBUS SCL, SDA, SMBA as AF I2C2/SMBUS TX, RX bxCAN1 TX, RX bxCAN2 DAC1_OUT as AF DAC2_OUT as AF ITF WWDG 4 KB BKSPRAM RTC_AF1 OSC32_IN OSC_IN OSC_OUT OSC32_OUT NRST VDDA, VSSA VCAP1, VCAP2 USART 6 RX, TX, CK, CTS, RTS as AF smcard irDA smcard irDA smcard irDA smcard irDA 16b 16b 32b 16b 16b 32b 16b 16b CTS, RTS as AF CTS, RTS as AF SDIO / MMC D[7:0] CMD, CK as AF VBAT = 1.65 to 3.6 V DMA1 AHB/APB1 DMA2 SCL, SDA, SMBA as AF I2C3/SMBUS GPIO PORT H PH[15:0] GPIO PORT I PI[11:0] JTAG & SW ARM Cortex-M3 120 MHz ART accelerator D-BUS S-BUS I-BUS NVIC ETM MPU NJTRST, JTDI, JTDO/SWD, JTDO TRACECLK TRACED[3:0] JTCK/SWCLK Ethernet MAC DMA/ MII or RMII as AF MDIO as AF FIFO 10/100 USB DMA/ FIFO OTG HS DP, DM ULPI: CK, D(7:0), DIR, STP, NXT DMA2 8 Streams FIFO DMA1 8 Streams FIFO SRAM 112 KB SRAM 16 KB CLK, NE [3:0], A[23:0] D[31:0], OEN, WEN, NBL[3:0], NL, NREG NWAIT/IORDY, CD NIORD, IOWR, INT[2:3] INTN, NIIS16 as AF SCL, SDA, INTN, ID, VBUS, SOF TDES, AES256 HASH RNG Camera interface HSYNC, VSYNC PIXCLK, D[13:0] USB OTG FS DP DM AHB1 120 MHz USART 2MBps Temperature sensor ADC1 ADC2 ADC 3 IF IF @VDDA @VDDA POR/PDR/ Supply @VDDA supervision PVD Reset Int P OR XTAL OSC 4-26 MHz XTAL 32 kHz MANAGT RTC RC HS RC LS PWR IWDG @V BAT @VDDA @VDD AWU Reset & clock control PLL1&2 interface VDD = 1.8 to 3.6 V VSS Voltage regulator 3.3 V to 1.2 V VDD12 Power managmt @VDD RTC_AF1 Backup register SCL/SDA, INTN, ID, VBUS, SOF AHB2 120 MHz 2 channels as AF 1 channel as AF 1 channel as AF TIM14 16b 16b 16b TIM9 2 channels as AF TIM10 1 channel as AF 16b 16b TIM11 1 channel as AF 16b BOR DAC1 DAC2 Flash 1 Mbyte SRAM, PSRAM, NOR Flash, PC Card (ATA), NAND Flash External memory controller (FSMC) TIM6 TIM7 TIM2 TIM3 TIM4 TIM5 TIM12 TIM13 ai15968d 4 compl. channels (TIM1_CH[1:4]N) 4 channels (TIM1_CH[1:4]), ETR, BKIN as AF AHB3 |
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