STM32F217VG datasheet(19/175 Pages) STMICROELECTRONICS

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DocID17050 Rev 9

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STM32F21xxx

Functional overview

174

Figure 5. Multi-AHB matrix

3.8

DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8

streams each. They are able to manage memory-to-memory, peripheral-to-memory and

memory-to-peripheral transfers. They share some centralized FIFOs for APB/AHB

peripherals, support burst transfer and are designed to provide the maximum peripheral

bandwidth (AHB/APB).

The two DMA controllers support circular buffer management, so that no specific code is

needed when the controller reaches the end of the buffer. The two DMA controllers also

have a double buffering feature, which automates the use and switching of two memory

buffers without requiring any special code.

Each stream is connected to dedicated hardware DMA requests, with support for software

trigger on each stream. Configuration is made by software and transfer sizes between

source and destination are independent.

ARM

Cortex-M3

DMA1

DMA2

MAC

Ethernet

USB OTG

Bus matrix-S

ICODE

DCODE

Flash

memory

SRAM

112 Kbyte

SRAM

16 Kbyte

AHB1

periph

AHB2

periph

FSMC

Static MemCtl

ai15963c

APB1

APB2

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