STM32F217VG datasheet(24/175 Pages) STMICROELECTRONICS

24 / 175 page

Functional overview

STM32F21xxx

24/175

DocID17050 Rev 9

Figure 6. Regulator OFF/internal reset ON

The following conditions must be respected:

•

VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection

between power domains.

•

If the time for VCAP_1 and VCAP_2 to reach 1.08 V is faster than the time for VDD to

reach 1.8 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and

VCAP_2 reach 1.08 V and until VDD reaches 1.8 V (see Figure 7).

•

Otherwise, If the time for VCAP_1 and VCAP_2 to reach 1.08 V is slower than the time for

VDD to reach 1.8 V, then PA0 should be asserted low externally (see Figure 8).

•

If VCAP_1 and VCAP_2 go below 1.08 V and VDD is higher than 1.8 V, then a reset must

be asserted on PA0 pin.

integrated power-on reset (POR)/ power-down reset (PDR) circuitry is disabled.

An external power supply supervisor should monitor both the external 1.2 V and the external

VDD supply voltage, and should maintain the device in reset mode as long as they remain

below a specified threshold. The VDD specified threshold, below which the device must be

maintained under reset, is 1.8 V. This supply voltage can drop to 1.7 V when the device

operates in the 0 to 70 °C temperature range. A comprehensive set of power-saving modes

allows to design low-power applications.

MS32736V1

REGOFF

VCAP_1

VCAP_2

PA0

1.2 V

VDD

(1.8 to 3.6 V)

Power-down reset risen

before VCAP_1/VCAP_2 stabilization

NRST

VDD

Application reset

signal (optional)

External VCAP_1/2

power supply supervisor

Ext. reset controller active

when VCAP_1/2 < 1.08 V

STM32F217VG 数据表(PDF) 24 Page - STMicroelectronics

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