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2.2.18 SYSTEM RESET (RESET)

This asynchronous active high input should be raised high

to reset the module. The high-to-low transition of this input will

start the module’s initialization.

2.2.19 START-UP ROM ENABLE (SURE)

This active high output goes high during initialization and

may also be asserted by software with the ESUR XIO

command. This signal remains high until removed by software

via the DSUR XIO command. When a Start-Up ROM is

present, this signal should be used to qualify its chip select or

output enable input such that the ROM may be accessed only

when SURE is high.

[NOTE: Instruction pipelining must be considered in

transitioning from Start-Up ROM to RAM when using the

DSUR XIO command. If a system overlays RAM with the Start-

Up ROM and transitions to execution from RAM by simply

executing DSUR from the ROM, then IA will contain the value

stored in the ROM location immediately following DSUR. This

value will be treated as an instruction and the module will

attempt to execute it. In such cases, it is recommended that

DSUR be followed by an unconditional branch instruction with

offset, i e, the BR instruction. An alternative approach is simply

to jump to a portion of RAM not overlaid by the Start-Up ROM

and execute DSUR from RAM.]

2.2.20 CONFIGURATION WORD (CONFW)

This active low output goes low when the module reads the

external configuration register and should be used as that

defines the required format of the configuration register. A zero

in a given bit position indicates the specified device is present.

Bits 0 through 11 are not used by the module.

The configuration register is read during initialization to

determine the system configuration. It is also read whenever a

(BPT) instruction is executed to determine the presence of a

Console. If a console is not present, a BPT will be interpreted

as a NOP. DDN goes low during a configuration register read.

Thus, the configuration register must reside on the system AD

bus rather than the local AD bus (see Figure 5).

2.2.21 NORMAL POWER UP (NPU)

This active high output is dropped low during module

initialization as the first step of BIT. If BIT is successful, NPU

goes high and remains high until reset by software via the RNS

XIO command. NPU cannot be set high by software.

2.2.22 TIMER CLOCK (TCLK)

This clock input is used by interval timers A and B as well

as the interface fault timer. Timer A is clocked at the TCLK

frequency while timer B is clocked at a frequency of TCLK/10.

MIL-STD-1750A requires that this input be a 100kHz pulse

train.

during execution of XIO commands which are implemented in

the MA31751 MMU(BPU) chip.

If an MA31751 is used with the MAS281, it must reside on

the MAS281 local AD bus rather than the system buses (see

Figure 5). Table 7b in Section 4.0 identifies those XIO

commands which are implemented in the MA31751].

2.2.13 DIRECT MEMORY ACCESS ENABLE (DMAE)

This active high output goes high in response to the DMAE

XIO command. A high state indicates DMA requests will be

acknowledged; a low state indicates a DMA request will be

ignored.

2.2.14 DIRECT MEMORY ACCESS REQUEST (DMAR)

A low on this asynchronous active low input will cause the

processor to suspend internal operations at the end of the

current machine cycle. This request will only be acknowledged

by the module when DMAE is high.

2.2.15 DIRECT MEMORY ACCESS ACKNOWLEDGE

(DMAK)

This active low signal goes low in response to a DMA

request if DMAE is high. A low state grants use of the system

busses to the requesting DMA device by placing the module’s

AD bus, AS, DSN,RD/WN, M/ION and IN/OPN drivers into the

high impedance state and by pulling CDN and DDN low. The

high-to-low transition is synchronized to the falling edge of

SYNCN to ensure that the current machine cycle is completed

before the DMA device is granted the bus. DMAKN will remain

low until the requesting device raises DMARN.

2.2.16 HOLD REQUEST (HOLD)

A low on this asynchronous active low input will cause the

module to suspend internal processor functions at the end of

the currently executing MIL-STD-1750A instruction. A Hold

state is also entered if the processor encounters a breakpoint

(BPT) instruction and the configuration word indicates the

presence of a Console (bit 15 = 0).

[Note: Hold should be syncronised to the AS signal.]

2.2.17 HOLD ACKNOWLEDGE (HLDAK)

This active low output goes low either upon completion of

the MIL-STD-1750A instruction during which HOLDN went low

or if the processor encounters a breakpoint (BPT) instruction

with Console present indicated in the configuration word

that that the module AD bus, AS, DSN, M/ION, RD/WN, and

IN/OPN drivers have been placed in the high impedance state.

The Hold state is terminated either by raising HOLDN high or,

in the case of a BPT caused Hold, by pulsing HOLDN low and

high again (see Section 6.0).

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