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MAS281 数据表(PDF) 23 Page - Dynex Semiconductor

部件名 MAS281
功能描述  MIL-STD-1750A Microprocessor
PDF  55 Pages
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制造商  DYNEX [Dynex Semiconductor]
网页  http://www.dynexsemi.com
标志 DYNEX - Dynex Semiconductor

MAS281 数据表(HTML) 23 Page - Dynex Semiconductor

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MAS281
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Operation
Op Code/Ext
Mnemonic
Format
Cycles *
LOGICAL
Inclusive Logical OR
E1
ORR
R
1
0
0
3X
ORB
B
2
1
0
4X F
ORBX
BX
2
1
0
E0
OR
D, DX
3
0
0
4A 8
ORIM
IM
2
0
0
Logical AND
E3
ANDR
R
1
0
0
3X
ANDB
B
2
1
0
4X E
ANDX
BX
2
1
0
E2
AND
D, DX
3
0
0
4A 7
ANDM
IM
2
0
0
Exclusive Logical OR
E5
XORR
R
1
0
0
E4
XOR
D, DX
3
0
0
4A 9
XORM
IM
2
0
0
Logical NAND
E7
NR
R
1
1
0
E6
N
D, DX
3
1
0
4A B
NIM
IM
2
1
0
Set Bit
51
SBR
R
1
0
0
50
SB
D, DX
4
1
0
52
SBI
I, IX
5
2
0
Reset Bit
54
RBR
R
1
1
0
53
RB
D, DX
4
1
0
55
RBI
I ,IX
5
2
0
Test Bit
57
TBR
R
1
0
0
56
TB
D, DX
3
0
0
58
TBI
I, IX
4
1
0
Test and Set Bit
59
TSB
D,DX
4
0
2
Set Variable Bit in Register
5A
SVBR
R
1
0
1
Reset Variable Bit in Register
5C
RVBR
R
1
1
1
Test Variable Bit in Register
5E
TVBR
R
1
0
1
Store Register Through Mask
97
SRM
D,DX
4
3
0
BYTE
Load From Upper Byte
8B
LUB
D,DX
3
0
0
8D
LUBI
I,IX
4
1
0
Load From Lower Byte
8C
LLB
D DX
3
1
0
8E
LLBI
I, IX
4
2
0
Store Into Upper Byte
9B
STUB
D,DX
4
1
0
9D
SUB I
I, IX
5
3
0
Store Into Lower Byte
9C
STLB
D,DX
4
1
0
9E
SLBI
I,IX
5
2
0
Exchange Bytes in Register
EC
XBR
S
1
0
1
* M = memory, P = processor (5 OSC cycles), B = processor (6 OSC cycles).
Table 7a: Instruction Summary (continued)
MP
B



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