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MAS281 数据表(PDF) 42 Page - Dynex Semiconductor

部件名 MAS281
功能描述  MIL-STD-1750A Microprocessor
PDF  55 Pages
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制造商  DYNEX [Dynex Semiconductor]
网页  http://www.dynexsemi.com
标志 DYNEX - Dynex Semiconductor

MAS281 数据表(HTML) 42 Page - Dynex Semiconductor

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NO.
Parameter
Test Condition
Min.
Max.
Units
(notes 1 & 9)
(note 2)
(note 2)
31
SYNC lo to DMAK valid
Load 1
-
50
ns
32
DMAK valid after SYNC lo
Load 1
5
-
ns
33
DMAK lo to DD lo
Load 1
-
30
ns
34
DMAK hi to DD hi
Load 1
-
30
ns
35
DMAK lo to CD lo
Load 1
-
30
ns
36
DMAK hi to CD hi
Load 1
-
30
ns
37
DMAK lo to AD Bus Hi-Z (note 7)
Load 2
-
70
ns
38
DMAK hi to AD Bus valid (note 10) Load 2
-
60
ns
39
DMAK lo to AS, DS, M/IO, RD/W,
IN/OP Hi-Z (note 7)
Load 2
-
50
ns
40
DMAK hi to AS, DS, M/IO,
RD/W, IN/OP valid (note 10)
Load 2
-
59
ns
41
HOLD set up to SYNC lo
40
-
ns
42
HOLD hold after SYNC lo
15
-
SYNC
43
SYNC lo to HLDAK valid
Load 1
-
20
ns
44
HLDAK valid after SYNC lo
Load 1
-7
-
ns
45
HLDAK lo to DD lo
Load 1
-
50
ns
46
HLDAK hi to DD hi
Load 1
-
50
ns
47
HLDAK lo to CD lo
Load 1
-
50
ns
48
HLDAK hi to CD hi
Load 1
-
50
ns
49
HLDAK lo to AD Bus Hi-Z
(Hold) (notes 7 & 10))
Load 2
-
60
ns
50
HLDAK hi to AD bus
valid (note 10)
Load 2
-
50
ns
51
HLDAK to AS, DS, M/IO,
RD/W, IN/OP Hi-Z (notes 7 & 10)
Load 2
-
30
ns
52
HLDAK to AS, DS, M/IO,
RD/W, IN/OP valid (note 10)
Load 1
-
30
ns
53
Interrupts set up to SYNC lo
20
-
ns
54
Interrupts hold after SYNC lo
10
-
ns
55
Faults setup to SYNC lo
20
-
ns
56
Faults hold after SYNC lo
15
-
ns
57
SYNC lo to SURE, NPU valid
Load 1
-
50
ns
58
SYNC hi to CONFW valid
Load 1
-
75
ns
59
TCLK lo to ILLAD lo (Bus timeout)
(note 10)
Load 1
-
75
ns
60
SYNC lo to ILLAD hi (Bus timeout)
(note 10)
Load 1
-
75
ns
Notes:
1. Unless otherwise noted, test conditions are as follows: OSC duty cycle = 50%, input rise and fall tlme < 5ns, timing
measured from 50% of VDD points.
2. t = 1 OSC period. O 5t implies a 50% OSC duty cycle; fractional t's may be adjusted to reflect actual OSC duty cycle.
7. Measured to pre-Hi-Z steady state
±10% of VDD.
9. Output references SYNC, DMAK, and HLDAK drive into load 1.
10. Guaranteed by component LSI testing: not measured on microprocessor module.
Table 10: Timing Parameters (continued)



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