MAS281 datasheet(10/55 Pages) DYNEX

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MAS281

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memory fault; bit 5 is set if it goes low during an l/O fault. As

with MPROEN, either condition immediately sets pending

interrupt level 1 and causes the currently executing MIL-STD-

1750A instruction to be aborted .

2.2.35 PROGRAMMED I/O TRANSFER ERROR (PIOXE)

A low on this active low input, captured by the SYNCN

high-to-low transition, is used to inform the module that a

programmed l/O data transfer error has been detected. Bit 6 of

the module Fault Register (FT) is set when this signal goes

low. This, in turn, causes pending interrupt level 1 to be set.

2.2.36 FAULT #7 (FLT7)

A low on this active low input, captured by the SYNCN

high-to-low transition, sets bit 7 of the Fault Register (FT). This

is a user definable fault.

2.2.37 SYSTEM FAULT (SYSF)

A low on this active low input, captured by the SYNCN

high-to-low transition, sets bits 13 and 15 of the Fault Register

(FT). This is a user definable fault.

2.2.38 ILLEGAL ADDRESS (ILLAD)

This active low output drops low if the EXADEN input drops

low or if the bus fault timeout circuit causes an interface

timeout.

2.2.39 MICROCODE STOP (MSTOP)

MSTOPN allows microcode to be single-stepped and is

reserved for use by GEC Plessey Semiconductors. MSTOPN

must be pulled up to VDD in customer applications.

2.2.40 ROM ONLY (ROMONLY)

ROMONLYN is used for testing by GEC Plessey

Semiconductors and must be pulled up to VDD in customer

applications.

3.0 OPERATING MODES

MAS281 operating modes include: (1) initialisation, (2)

instruction execution, (3) interrupt servicing, (4) fault servicing,

(5) DMA support, (6) Hold support, and (7) timer operations.

3.1 INITIALISATION

The module executes a microcoded initialisation routine in

response to a hardware reset. This routine clears module

registers, disables and masks interrupts, reads the

configuration register, resets the output discrete register (if

implemented), initialises the MMU and BPU (if implemented),

performs Built-ln-Test (BIT), raises the Start-Up ROM enable

discrete, clears and starts timers A and B, resets the trigger-go

counter, and loads the instruction pipeline. Table 2

summarises the resulting initialisation state, and Table 3

provides a detailed breakdown of the initialisation sequence.

BIT consists of five subroutines, as outlined in table 4, and

begins by pulling NPU low. This is the first time after reset that

NPU is guaranteed low. If all five subroutines execute

successfully, NPU is raised high. If any part of BIT fails, an

error code identifying the failed subroutine is loaded into the

Fault Register (FT), BIT is aborted, and NPU is left in the low

state. Table 4 defines the coding of BIT results in FT. In the

event of such a failure, the resulting module reset state will be

dependent on where in BIT the error occurred and may not be

the same as that shown in Table 2. A BIT failure indication in

FT will set the level 1 interrupt request bit of the Pending

Interrupt (Pl) register. Since initialisation disables and masks

interrupts, this interrupt request will not be asserted .

The last action performed by the initialisation routine is to

load the instruction pipeline. Instruction fetches start at

memory location zero and will be from the Start-Up ROM if

implemented. Whether BIT passes or not, the processor will

begin instruction execution at this point.The system start-up

code may include a routine to enable and unmask interrupts in

order to detect and respond to a BIT failure.

[NOTE: To complete initialisation and pass BIT, interrupt

and fault inputs must be high for the duration of the

initialisation routine. Also, timers A and B must be clocked

during this interval, i.e., TCLK must be applied.]

MAS281

Instruction Counter (IC)

Zeroed

Status Word (EU and MMU) (SW) Zeroed

Fault (FT)

Zeroed

Pending Interrupt (PI)

Zeroed

Mask (MK)

Zeroed

Interrupts

Disabled

DMA Access

Disabled

Timer A

Reset and Started

Timer B

Reset and Started

Trigger-Go Timer

Reset and Started

MMU

Page Registers

Group 0 Enabled

AL, W, E Fields

Zeroed

PPA Field

Logical to Physical

Map

BPU

Write Protect

Zeroed

Global Memory Protect

Enabled

Table 2: Initialisation State

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