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MAS281 数据表(PDF) 43 Page - Dynex Semiconductor

部件名 MAS281
功能描述  MIL-STD-1750A Microprocessor
PDF  55 Pages
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制造商  DYNEX [Dynex Semiconductor]
网页  http://www.dynexsemi.com
标志 DYNEX - Dynex Semiconductor

MAS281 数据表(HTML) 43 Page - Dynex Semiconductor

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NO.
Parameter
Test Condition
Min.
Max.
Units
(notes 1 & 9)
(note 2) (note 2)
61
SURE, NPU, ILLAD, CONFW
valid after SYNC lo (note 10)
Load 1
5
-
ns
62
TGCLK lo to TGO lo (Timer clocking) (note 10)
Load 1
-
150
ns
63
SYNC hi to TGO hi
(Reset Trigger-Go XIO) (note 10)
Load 1
-
75
ns
64
TCLK setup to SYNC lo (note 10)
30
-
ns
65
TCLK hold after SYNC lo (note 10)
10
-
ns
66
DTIMER setup to SYNC lo (note 10)
50
-
ns
67
DTIMER hold after SYNC lo (note 10)
10
-
ns
68
DTIMER setup to TGCLK hi (note 10)
30
-
ns
69
DTIMER hold after TGCLK lo (note 10)
12
-
ns
70
DTO setup to TCLK lo (note 10)
30
-
ns
71
DTO hold after TCLK lo (note 10)
10
-
ns
72
DTIMER lo to DMAE lo (note 10)
Load 1
-
60
ns
73
DTIMER hi to DMAE normal operation (note 10) Load 1
-
60
ns
74
TCLK lo to Normal operation after
bus timeout (note 10)
-
100
ns
75
EXADE lo to ILLAD lo (note 10)
Load 1
-
60
ns
76
EXADE hi to ILLAD hi (note 10)
Load 1
-
60
ns
77
SYNC lo to DD hi (Internal to XIO) (note 3, 10)
Load 1
-
60
ns
78
Bus fault timeout interval (note 3, 10)
1
2
TCLK
79
DD hi to AS lo (DMA) (note 3, 10)
Load 1
20
-
ns
80
DS hi to Data valid (note 10)
Load 1 (DS),
15
-
ns
Load 2 (Data)
Notes:
1. Unless otherwise noted, test conditions are as follows: OSC duty cycle = 50%, input rise and fall time < 5ns, timing measured
from 50% of VDD points.
2. t = 1 OSC period 0.5t implies a 50% OSC duty cycle; fractional t's may be adjusted to reflect actual OSC duty cycle
3. Data obtained by characterisation or analysis, is not routinely measured.
9. Output references SYNC, DMAK, and HLDAK drive into load 1.
10. Guaranteed by component LSI testing: not measured on microprocessor module.
Table 10: Timing Parameters (continued)



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