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Interrupt

Address

PWRD

122

INT02

326

428

52A

62C

72E

2 F

INT08

932

INT10

INT11

IOI1

INT13

IOI2

INT15

Table 5: Interrupt Pointer Definitions

Figure 6: Interrupt Vectoring

interrupts are output to the priority encoder where the highest

priority is encoded as a 4-bit vector. If interrupts are enabled,

and an unmasked interrupt is pending, the priority encoder will

assert an interrupt request to the CU.

Upon completing execution of a given MIL-STD-1750A

instruction, the CU’s microsequencer checks the state of the

priority encoder’s interrupt request. If an interrupt request is

asserted, the microsequencer branches to the microcode

interrupt service routine. This routine performs a read of the

priority encoder’s 4-bit pending interrupt vector, stores the

value in the EU Dl register, and then uses this value to

calculate the appropriate interrupt linkage and service

pointers. The pointers serve as addresses to data structures

used in servicing interrupts. Figure 6 depicts this relationship.

Table 5 defines pointer values.

Using the linkage and service pointers, the microcode

interrupt service routine performs the following: (1) the current

contents of the status word, mask register, and instruction

counter are saved; (2) a write status word l/O command is

executed with an all zero data word; (3) the new mask is

loaded into MK and interrupts are disabled; (4) the new status

word is read and checked for a valid AS field - If AS is non-zero

and an MMU is not present, AS is set to zero and fault 11

(address state error) is set in the fault register FT; (5) a write

status word command using the new status word is performed;

and (6) the new IC value is loaded into IC, the instruction

pipeline is filled starting at the new address, and instruction

execution begins.

[NOTE: The steps listed above represent a summary of

actions performed during interrupt servicing and do not

necessarily reflect the actual order in which these events take

place.]

If an interrupt is latched during the interrupt service routine,

it will not be processed until interrupts are re-enabled. If an AS

fault occurs during the service routine, interrupt level 1 will be

set. This interrupt will be serviced when interrupts are re-

enabled unless it is masked by the new value in MK.

3.4 FAULT SERVICING

Eight user fault inputs are provided. A low on any of these

inputs will be latched into the Fault Register (FT) at the high-to-

low transition of SYNCN.

exception of INT02N which is latched into Pl when INT02N is

first detected). This sequence occurs whether interrupts are

enabled or disabled or whether the specific interrupt is masked

or unmasked.

Each external Pl register input is buffered by a falling edge

detector to prevent repeat latching of requests held low

beyond the first SYNCN high-to-low transition. An interrupt

request input must transition to the high state before a

subsequent request on that input will be detected.

When an interrupt request is latched into Pl, it is ANDed

with its corresponding mask bit in the mask register (MK).

Interrupt level 0 is not maskable. Any unmasked pending

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