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or more faults in FT will cause a level 1 (machine error)

interrupt request. Once a fault is set in FT, it may only be

cleared via an XIO command.

1.3.5 TIMERS A AND B

These are two 16-bit software controllable timers. Timer A

is clocked by the TCLK input while Timer B is clocked by the

internally generated TCLK/10. Timers A and B will generate

interrupt levels 7 and 9, respectively, when their maximum

counts of 65,536 are reached.

1.3.6 TRIGGER-GO COUNTER

This 16-bit counter is clocked by the TGCLK input, is

enabled during system initialisation, and may be reset but not

stopped by software action. It is stopped, however, upon

overflow or by assertion of the DTIMERN input. Upon overflow,

the TGON discrete output goes low and stays low until the

counter is reset by software. This counter is typically used as a

system “watchdog" timer.

1.3.7 XIO COMMAND DECODE LOGIC

This logic decodes all internally supported XlO commands

and generates the control signals necessary to carry out the

commanded action. An internal ready signal is generated upon

command detection and is used by the EU state sequencer as

previously discussed. Table 7b in Section 4.0 identifies the XlO

commands which are internally supported by the MAS281.

1.3.8 MICROCODE CONTROL LOGIC

Decode logic, which translates microcode received from

the CU into control signals, is used both by the MAS281 and by

the external system.

2.0 INTERFACE SIGNALS

2.1 PIN ASSIGNMENTS

Figure 4 defines the pin assignment for the MAS281

module. See section 10.0 for full packaging and pin

assignment information.

All signals - with the exception of power, ground and

ROMONLYN - are TTL compatible. In addition, each function

is provided with Electrostatic Discharge (ESD) protection

circuitry. Figure 5 depicts a typical system implementation

using many of these signals. Throughout this data sheet,

active low signals are denoted either by placing a bar over the

signal name, or by following the signal name with an “N” suffix,

e.g., DDN. If a signal has a dual function, both function names

will be used separated by a “/”. The function name to the left of

the “/” will be active high while the function to the right will be

active low, again with an “N" suffix, e g., RD/WN.

1.2.2 MICROCODE ROM

This is a 2k- (2048) word by 40-bits/word ROM which

stores the microinstructions that implement the MIL-STD-

1750A instruction set. The address of the next microinstruction

to be accessed is generated by the microsequencer. The

accessed microinstruction is output to the M-bus and

broadcast to the EU and IU. In addition to the microinstruction

sequences corresponding to the MIL-STD-1750A instructions,

the microcode ROM also stores sequences for performing

initialisation, interrupt response, Hold response, instruction

prefetch, built-intest (BIT), and BlFs.

1.2.3 INSTRUCTION MAPPING ROM

This is a 512-word by 8-bits/word ROM which is used

during microcode branches.

1.3 INTERRUPT UNIT (IU)

The IU incorporates a pending interrupt register, a mask

(A and B), a trigger-go counter, XIO command decode logic,

and microcode control logic. A brief description of these

features follows:

1.3.1 PENDING INTERRUPT REGISTER (PL)

This 16-bit register is used to capture and hold interrupts

until they can be processed by software. Pl supports three

dedicated external, six user-definable external, and seven

dedicated internal interrupts. Interrupts are captured at the

beginning of each machine cycle and are stored using a logic 1

to represent a pending interrupt. Anti-repeat logic is provided

to prevent multiple captures of the same interrupt.

1.3.2 MASK REGISTER (MK)

This 16-bit register is used to store the interrupt mask.

Interrupts are masked by ANDing each mask bit with its

corresponding Pl register bit. Interrupts which are masked will

be captured in the Pl register but will not be acted on until

unmasked. Interrupt level 0 can not be masked. A logic 0 in a

given bit position indicates that the corresponding bit in the Pl

1.3.3 PRIORITY ENCODER

This encoder generates an interrupt request to the CU

whenever one or more unmasked interrupts are pending and

enabled in the Pl and encodes the highest priority unmasked

pending interrupt as a 4-bit vector. This vector is read by the

EU over the AD bus during interrupt servicing in order to create

the interrupt Linkage and Service pointers.

1.3.4 FAULT REGISTER

This 16-bit register is used to capture and hold both internal

and user implemented external faults. Faults are captured at

the beginning of each machine cycle and are stored using

positive logic, i e, a logic “1” represents a fault. Setting any one

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