MAS281 datasheet(4/55 Pages) DYNEX

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MAS281

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1.1.7 OPERAND TRANSFER REGISTERS

The Address (A), Data In (Dl), and Data Out (DO) registers

serve to buffer transfers between the data path and the

Address/Data (AD) bus. These registers are used under

microcode control and are not directly accessible by software.

A description of the use of these registers during memory and

l/O operations is provided in section 3.0.

1.1.8 INSTRUCTION FETCH REGISTERS

The Instruction Counter (IC), Instruction A (IA), and

Instruction B (IB) registers allow sequential instruction fetches

to be performed without the assistance of the ALU. The IC

instruction to be fetched, is loaded indirectly via reset, jump, or

branch operations. Once loaded, it uses a dedicated counter to

sequence from one instruction to the next. IA and IB serve as

an instruction pipeline with IA storing the next instruction to be

executed. Dl also plays a role by storing any immediate

operands. Use of these registers during instruction fetches is

described in section 3.0.

1.1.9 MICROCODE CONTROL LOGIC

All EU operations are performed under microcode control.

As depicted in Figure 2, microinstructions are provided by the

CU over the M bus, buffered by the Execution (E) register, and

decoded to generate various control signals.

1.2 CONTROL UNIT (CU)

The CU provides microprogrammed control of all MAS281

operations. It features a microsequencer, a microcode storage

ROM, and an instruction mapping ROM. A brief description of

these features follows:

1.2.1 MICROSEQUENCER

This 12-bit wide microcode address generator controls all

microcode ROM accesses. The microsequencer features a

program counter (PC) which points to the next sequential

microinstruction, a program counter save register (SV) to save

return addresses for microsubroutines, address increment

logic (INCR), instruction pipeline registers (IA and IB), a next

address multiplexer, a loop counter (C), and various

miscellaneous systems.

The microsequencer controls the execution of each

MILSTD-1750A, or macro, instruction by stepping through its

corresponding microcode sequence. If the macroinstruction is

a conditional, the CS bits of the status word will be interrogated

to determine the necessary course of action. At the completion

of each macroinstruction, the microsequencer checks to see if

a Hold request or an interrupt is pending. If so, the

microsequencer will branch to the appropriate microinstruction

sequence. If not, the microsequencer begins sequencing the

next macroinstruction.

Note that the microsequencer is itself under the control of

the EU state sequencer. Each processor machine cycle

corresponds to the execution of a single microinstruction.

A machine cycle requires five or more oscillator cycles

with the exact number determined by the type of operation

being performed. Internal processor operations, excluding

internally decoded XIO commands, require either five or six

oscillator cycles, the former associated with sequential

microcode execution and the latter with microcode branches.

Internally decoded XIO commands require a minimum of six

oscillator cycles to complete. External processor operations

require a minimum of five oscillator cycles to complete.

The internal ready signal is generated by the IU whenever

an internally decoded XIO command is detected An external

ready interface is provided which allows external machine

cycles to be extended when interfacing with slow devices. The

external ready signal is provided by external logic and must be

asserted in order to conclude the machine cycle.

Field

Bits

Description

CONDITION STATUS:

C-

Carry from an

addition or no borrow from

a subtraction

P-

Result >0

Z-

Result = 0

N-

Result<0

4 - 7

RESERVED

8 - 11

PROCESSOR STATE:

(a)- Memory access key

code

(b)- Privileged instruction

enable

12 - 15

ADDRESS STATE:

Page register sets for

expanded memory

addressing

Figure 3: Status Word Format

3 4

7 8

11 12

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