MAS281 datasheet(17/55 Pages) DYNEX

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MAS281

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l/O) of the Fault Register (FT) is set. This sets pending

interrupt level 1 and causes the current bus cycle to be

terminated by forcing SYNCN low. The MIL-STD-1750A

instruction is aborted, and control passes to the level 1

interrupt service routine (if the level 1 interrupt is unmasked).

This feature is disabled by pulling DTON low.

4. SOFTWARE CONSIDERATIONS

The MAS281 implements the full MIL-STD-1750A

instruction set. Table 7a lists the instruction set and provides

performance data for each instruction. Table 7b provides a

summary of the XIO commands which are internally decoded

on the module. Resources available to the software

programmer are depicted in Figure 9. A discussion of data

types, addressing modes and benchmarking considerations

follows.

4.1 DATA TYPES

The MAS281 fully supports 16-bit fixed-point single

precision, 32-bit fixed-point double-precision, 32-bit floating-

point, and 48-bit extended precision floating point data types.

Figure 10 depicts the formats of these data types.

All numerical data is represented in two’s complement

form. Floating-point numbers are represented by a fractional

two’s complement mantissa with an 8-bit two’s complement

exponent. All floating-point operands are expected to be

normalized. If not normalized, the results from an instruction

are not defined.

4.2 ADDRESSING MODES

The MAS281 supports the eight addressing modes

specified in MIL-STD-1750A. These addressing modes are

depicted in Figure 11 and are defined below.

4.2.1 REGISTER DIRECT (R)

The register specified by the instruction contains the

required operand.

4.2.2 MEMORY DIRECT (D,DX)

Memory Direct (without indexing) is an addressing mode in

which the instruction contains the memory address of the

required operand. In Memory Direct-lndexed (DX), the

memory address of the required operand is specified by the

sum of the contents of an index register (RX) and the

instruction address field (A). Register R1 through R15 may be

specified for indexing.

4.2.3 MEMORY INDIRECT (I, IX)

Memory Indirect (without indexing) is an addressing mode

in which the memory address specified by the instruction

contains the address of the required operand. In Memory

Indirect with Pre-lndexing (IX), the sum of the contents of a

specified index register and the instruction address field in the

address that contains the address of the required operand.

Registers R1 through R15 may be specified for pre-indexing.

Hold state. Again pulling HOLDN will cause the next instruction

to execute. This process may be repeated as long as required.

Raising HOLDN high will resume normal operatlon.

3.7 TIMER OPERATIONS

The MAS281 implements interval timers A and B, a trigger-

go counter, and a bus fault timer. A discussion of each follows:

3.7.1 TIMERS A AND B

Timer A is clocked by the TCLK input; timer B is clocked by

an internally generated TCLK/10. MIL-STD-1750A requires

TCLK to be a 100-kHz pulse train. If allowed to overflow, timers

A and B will set level 7 and level 9 interrupt requests,

respectively. Timing characteristics of each timer are defined

in Section 5.0. Either timer can be read, loaded, started, and

stopped through the use of internally decoded XIO commands.

These commands are identified in Table 7b in Section 4.0.

By asserting the DTIMERN input, both timers will halt and all

internally decoded XIO commands which would change their

state are disabled (asserting DTIMERN also disables DMA

accesses by driving DMAE low and DMAKN high). Raising

DTIMERN allows the timers to resume counting from their

suspended state and allows timer commands to function

normally (DMA control lines are again allowed to change).

A feature of the MAS281 timers is the choice of disabling,

or not disabling, the interval timers A and B upon execution of

a BPT software instruction when a Console is connected. If full

compliance with MIL-STD-1750 (Notice 1) is desired, the

halting of timers A and B can be accomplished by pulling

DTIMERN low upon execution of a BPT instruction with a

Console connected. Two suggested ways to do this are: (1)

connect HLDAKN to DTIMERN through an AND gate; or (2)

allow the system Console to pull DTIMERN low upon receiving

HLDAKN low. The first option provides a faster response and

is a less complicated method, whereas the second choice

allows the option of halting timers A and B, or not halting them.

[NOTE: As described in Section 2.2, DTIMERN low

suspends the trigger-go timer and disables DMA access

(forces DMAE low and DMAKN high) in addition to halting

timers A and B].

3.7.2 TRIGGER-GO COUNTER

The trigger-go counter is clocked by the TGCLK input.

Timing characteristics for trigger-go counter operation are

defined in Section 6 0. DTIMERN disables and enables

operation in the same manner as with timers A and B.

Whenever the trigger-go counter overflows, TGON drops low

and remains low until the counter is reset via the GO internal

XIO command.

3.7.3 BUS FAULT TIMER

All bus operations are monitored to ensure timely

completion. A hardware timeout circuit is enabled at the start of

each memory and l/O transfer (DSN high-to-low transition) and

is reset upon receipt of the external ready (RDYN) signal.

If this circuit fails to reset within a minimum of one TCLK

period or a maximum of two TCLK periods, either bit 8 (if the

transaction is with memory) or bit 5 (if the transaction is with

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