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WM8960 数据表(PDF) 45 Page - Wolfson Microelectronics plc |
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WM8960 数据表(HTML) 45 Page - Wolfson Microelectronics plc |
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45 / 92 page ![]() Production Data WM8960 w PD, August 2013, Rev 4.2 45 HEADPHONE JACK DETECT The ADCLRC/GPIO1, LINPUT3/JD2 and RINPUT3/JD3 pins can be selected as headphone jack detect inputs to automatically disable the speaker output and enable the headphone output e.g. when a headphone is plugged into a jack socket. In this mode, enabled by setting HPSWEN, the headphone detect input pin switches between headphone and speaker outputs (e.g. when the pin is connected to a mechanical switch in the headphone socket to detect plug-in). The HPSEL[1:0] bits select the input pin used for this function. The HPSWPOL bit reverses the pin’s polarity. Note that the LOUT1, ROUT1, SPKL and SPKR bits in register 26 must also be set for headphone and speaker output (see Table 29 and Table 30). TOEN must also be set to enable the clock which is used for de-bouncing the jack detect input. TOCLKSEL selects a fast or slow de-bounce period. Note that SYSCLK must be enabled to use this function. When using capless mode, the OUT3CAP bit should be enabled so that OUT3 is enabled/disabled at the same time as HP_L and HP_R to prevent pop noise. The debounced headphone detect signal can also be output to the ADCLRC/GPIO1 pin (See GPIO section). This function is not available when using GPIO1 as an input or as ADCLRC. When using the ADCLRC/GPIO1 pin as a headphone detect input, the ALRCGPIO register bit needs to be set to 1. In this mode, DACLRC is used for both ADC and DAC frame clocks. (See GPIO section for more information) Note: When LINPUT3 or RINPUT3 is used as the headphone detect input, the thresholds become CMOS levels (0.3 AVDD / 0.7 AVDD). HPSWEN HPSWPOL HEADPHONE DETECT PIN (LINPUT3/JD2, RINPUT3/JD3 OR ADCLRC/GPIO1) L/ROUT1 (AND OUT3 IN CAPLESS MODE) (REG. 26) SPKL/R (REG. 26) HEADPHONE ENABLED (AND OUT3 IN CAPLESS MODE) SPEAKER ENABLED 0 X X 0 0 no no 0 X X 0 1 no yes 0 X X 1 0 yes no 0 X X 1 1 yes yes 1 0 0 X 0 no no 1 0 0 X 1 no yes 1 0 1 0 X no no 1 0 1 1 X yes no 1 1 0 0 X no no 1 1 0 1 X yes no 1 1 1 X 0 no no 1 1 1 X 1 no yes Table 29 Headphone Jack Detect Operation REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R24 (18h) Additional Control (2) 6 HPSWEN 0 Headphone Switch Enable 0 = Headphone switch disabled 1 = Headphone switch enabled 5 HPSWPOL 0 Headphone Switch Polarity 0 = HPDETECT high = headphone 1 = HPDETECT high = speaker |
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