WM8960 datasheet(49/92 Pages) WOLFSON

49 / 92 page

Production Data

WM8960

PD, August 2013, Rev 4.2

BCLK DIVIDE

The BCLK frequency in master mode is controlled by BCLKDIV[3:0]. When the ADCs and DACs are

operating at different sample rates, BCLKDIV must be set appropriately to support the data rate of

whichever is the faster.

Internal clock divide and phase control mechanisms ensure that the BCLK, ADCLRC and DACLRC

edges will occur in a predictable and repeatable position relative to each other and to the data for a

given combination of DAC sample rate, ADC sample rate and BCLKDIV settings.

See Clocking and Sample Rates section for more information.

AUDIO DATA FORMATS

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

Figure 26 Left Justified Audio Interface (assuming n-bit word length)

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK

transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.

Figure 27 Right Justified Audio Interface (assuming n-bit word length)

In I

2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.

The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and

the MSB of the next.

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