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WM8960 数据表(PDF) 67 Page - Wolfson Microelectronics plc

部件名 WM8960
功能描述  Stereo CODEC with 1W Stereo Class D Speaker Drivers and Headphone Drivers for Portable Audio Applications
PDF  92 Pages
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制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8960 数据表(HTML) 67 Page - Wolfson Microelectronics plc

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Production Data
WM8960
w
PD, August 2013, Rev 4.2
67
REGISTER MAP
REGISTER
remarks
Bit[8]
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
default
R0 (00h)
Left Input volume
IPVU
LINMUTE
LIZC
0_1001_0111
R1 (01h)
Right Input volume
IPVU
RINMUTE
RIZC
0_1001_0111
R2 (02h)
LOUT1 volume
OUT1VU
LO1ZC
0_0000_0000
R3 (03h)
ROUT1 volume
OUT1VU
RO1ZC
0_0000_0000
R4 (04h)
Clocking (1)
CLKSEL
0_0000_0000
R5 (05h)
ADC & DAC Control (CTR1)
0
DACDIV2
0
DACMU
ADCHPD
0_0000_1000
R6 (06h)
ADC & DAC Control (CTR2)
0
0
0
DACSMM
DACMR
DACSLOPE
0
0_0000_0000
R7 (07h)
Audio Interface
ALRSWAP
BCLKINV
MS
DLRSWAP
LRP
0_0000_1010
R8 (08h)
Clocking (2)
00
1_1100_0000
R9 (09h)
Audio Interface
0
0
ALRCGPIO
WL8
LOOPBACK
0_0000_0000
R10 (0Ah)
Left DAC volume
DACVU
0_1111_1111
R11 (0Bh)
Right DAC volume
DACVU
0_1111_1111
R12 (0Ch)
Reserved
0
0
0
0
0
0
0
0
0
0_0000_0000
R13 (0Dh)
Reserved
0
0
0
0
0
0
0
0
0
0_0000_0000
R14 (0Eh)
Reserved
0
0
0
0
0
0
0
0
0
0_0000_0000
R15 (0Fh)
Reset
not reset
R16 (10h)
3D control
0
0
3DUC
3DLC
3DEN
0_0000_0000
R17 (11h)
ALC1
0_0111_1011
R18 (12h)
ALC2
1
0
1_0000_0000
R19 (13h)
ALC3
ALCMODE
0_0011_0010
R20 (14h)
Noise Gate
0
0
0
NGAT
0_0000_0000
R21 (15h)
Left ADC volume
ADCVU
0_1100_0011
R22 (16h)
Right ADC volume
ADCVU
0_1100_0011
R23 (17h)
Additional control(1)
TSDEN
0
DMONOMIX
TOCLKSEL
TOEN
1_1100_0000
R24 (18h)
Additional control(2)
0
0
HPSWEN
HPSWPOL
0
TRIS
LRCM
0
0
0_0000_0000
R25 (19h)
Pwr Mgmt (1)
VREF
AINL
AINR
ADCL
ADCR
MICB
DIGENB
0_0000_0000
R26 (1Ah)
Pwr Mgmt (2)
DACL
DACR
LOUT1
ROUT1
SPKL
SPKR
0
OUT3
PLL_EN
0_0000_0000
R27 (1Bh)
Additional Control (3)
0
0
VROI
0
0
OUT3CAP
0_0000_0000
R28 (1Ch)
Anti-pop 1
0
POBCTRL
0
0
BUFDCOPEN
BUFIOEN
SOFT_ST
0
HPSTBY
0_0000_0000
R29 (1Dh)
Anti-pop 2
0
0
DISOP
0
0
0
0
0_0000_0000
R30 (1Eh)
Reserved
0
0
0
0
0
0
0
0
0
0_0000_0000
R31 (1Fh)
Reserved
0
0
0
0
0
0
0
0
0
0_0000_0000
R32 (20h)
ADCL signal path
LMN1
LMP3
LMP2
LMIC2B
0
0
0
1_0000_0000
R33 (21h)
ADCR signal path
RMN1
RMP3
RMP2
RMIC2B
0
0
0
1_0000_0000
R34 (22h)
Left out Mix (1)
LD2LO
LI2LO
0
0
0
0
0_0101_0000
R35 (23h)
Reserved
0
0
1
0
1
0
0
0
0
0_0101_0000
R36 (24h)
Reserved
0
0
1
0
1
0
0
0
0
0_0101_0000
R37 (25h)
Right out Mix (2)
RD2RO
RI2RO
0
0
0
0
0_0101_0000
R38 (26h)
Mono out Mix (1)
0
L2MO
0
0
0
0
0
0
0
0_0000_0000
R39 (27h)
Mono out Mix (2)
0
R2MO
0
0
0
0
0
0
0
0_0000_0000
R40 (28h)
LOUT2 volume
SPKVU
SPKLZC
0_0000_0000
R41 (29h)
ROUT2 volume
SPKVU
SPKRZC
0_0000_0000
R42 (2Ah)
MONOOUT volume
0
0
MOUTVOL
0
0
0
0
0
0
0_0100_0000
R43 (2Bh)
Input boost mixer (1)
0
0
0
0_0000_0000
R44 (2Ch)
Input boost mixer (2)
0
0
0
0_0000_0000
R45 (2Dh)
Bypass (1)
0
LB2LO
0
0
0
0
0_0101_0000
R46 (2Eh)
Bypass (2)
0
RB2RO
0
0
0
0
0_0101_0000
R47 (2Fh)
Pwr Mgmt (3)
0
0
0
LMIC
RMIC
LOMIX
ROMIX
0
0
0_0000_0000
R48 (30h)
Additional Control (4)
0
GPIOPOL
TSENSEN
MBSEL
0_0000_0010
R49 (31h)
Class D Control (1)
0
1
1
0
1
1
1
0_0011_0111
R50 (32h)
Reserved
0
0
1
0
0
1
1
0
1
0_0100_1101
R51 (33h)
Class D Control (3)
0
1
0
0_1000_0000
R52 (34h)
PLL N
SDM
PLLRESCALE
0_0000_1000
R53 (35h)
PLL K 1
0
0_0011_0001
R54 (36h)
PLL K 2
0
0_0010_0110
R55 (37h)
PLL K 3
0
0_1110_1001
LINVOL[5:0]
RINVOL[5:0]
LOUT1VOL[6:0]
ROUT1VOL[6:0]
ADCDIV[2:0]
DACDIV[2:0]
SYSCLKDIV[1:0]
ADCPOL[1:0]
DEEMPH[1:0]
DACPOL[1:0]
WL[1:0]
FORMAT[1:0]
DCLKDIV[2:0]
BCLKDIV[3:0]
writing to this register resets all registers to their default state
3DDEPTH[3:0]
DACCOMP[1:0]
ADCCOMP[1:0]
LDACVOL[7:0]
RDACVOL[7:0]
DCY[3:0]
ATK[3:0]
NGTH[4:0]
ALCSEL[1:0]
MAXGAIN[2:0]
ALCL[3:0]
MINGAIN[2:0]
HLD[3:0]
VMIDSEL[1:0]
ADC_ALC_SR[2:0]
LADCVOL[7:0]
RADCVOL[7:0]
VSEL[1:0]
DATSEL[1:0]
RI2ROVOL[2:0]
SPKLVOL[6:0]
LMICBOOST[1:0]
RMICBOOST[1:0]
LI2LOVOL[2:0]
RB2ROVOL[2:0]
GPIOSEL[2:0]
HPSEL[1:0]
SPKRVOL[6:0]
LIN3BOOST[2:0]
LIN2BOOST[2:0]
RIN3BOOST[2:0]
RIN2BOOST[2:0]
DRES[1:0]
PLLK[23:16]
PLLK[15:8]
PLLK[7:0]
DCGAIN[2:0]
ACGAIN[2:0]
OPCLKDIV[2:0]
PLLN[3:0]
SPK_OP_EN[1:0]
LB2LOVOL[2:0]



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