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WM8960 数据表(PDF) 60 Page - Wolfson Microelectronics plc

部件名 WM8960
功能描述  Stereo CODEC with 1W Stereo Class D Speaker Drivers and Headphone Drivers for Portable Audio Applications
PDF  92 Pages
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制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8960 数据表(HTML) 60 Page - Wolfson Microelectronics plc

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WM8960
Production Data
w
PD, August 2013, Rev 4.2
60
DEEMPH, 3DUC and 3DUC should be configured to match the chosen DAC sample rate.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R27 (1Bh)
Additional Control
(3)
2:0
ADC_ALC_SR
[2:0]
000
ALC Sample Rate
000 = 44.1k / 48k
001 = 32k
010 = 22.05k / 24k
011 = 16k
100 = 11.25k / 12k
101 = 8k
110 and 111 = Reserved
R5 (05h)
ADC and DAC
Control (1)
2:1
DEEMPH
[1:0]
00
De-Emphasis Control
11 = 48kHz sample rate
10 = 44.1kHz sample rate
01 = 32kHz sample rate
00 = No de-emphasis
R16 (10h)
3D Enhance
6
3DUC
0
Upper Cut-Off Frequency
0 = High (Recommended for
fs>=32kHz)
1 = Low (Recommended for
fs<32kHz)
5
3DLC
0
Lower Cut-Off Frequency
0 = Low (Recommended for
fs>=32kHz)
1 = High (Recommended for
fs<32kHz)
Table 42 Additional Sample Rate Controls
PLL
The integrated PLL can be used to generate SYSCLK for the WM8960 or provide clocking for external
devices via the GPIO1 pin.
The PLL is enabled by the PLLEN register bit.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R26 (1Ah)
Power
management (2)
0
PLLEN
0
PLL Enable
0 = PLL off
1 = PLL on
R52 (34h)
PLL (1)
5
SDM
0
Enable Integer Mode
0 = Integer mode
1 = Fractional mode
Table 43 PLLEN Control Bit
The PLL frequency ratio R = f2/f1 (See Figure 36) can be set using the register bits PLLK and PLLN:
PLLN = int R
PLLK = int (2
24 (R-PLLN))
EXAMPLE:
MCLK=12MHz, required clock = 12.288MHz.
R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a selectable
divide by N after the PLL which should be set to divide by 2 to meet this requirement.
Enabling the divide by 2 sets the required f2 = 4 x 2 x 12.288MHz = 98.304MHz.
R = 98.304 / 12 = 8.192
PLLN = int R = 8
k = int ( 2
24 x (8.192 – 8)) = 3221225 = 3126E9h



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