| 数据搜索系统,热门电子元器件搜索 |
|
WM8960 数据表(PDF) 13 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8960 数据表(HTML) 13 Page - Wolfson Microelectronics plc |
|
13 / 92 page ![]() Production Data WM8960 w PD, August 2013, Rev 4.2 13 SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING Figure 2 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD1=SPKVDD2=3.3V, DGND=AGND=SPKGND1=SPKGND2=0V, TA = +25 oC PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT System Clock Timing Information MCLK cycle time TMCLKY 33.33 ns MCLK duty cycle TMCLKDS 60:40 40:60 AUDIO INTERFACE TIMING – MASTER MODE Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface) MCLK tMCLKY |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |