WM8960 datasheet(14/92 Pages) WOLFSON

部件名	WM8960

功能描述	Stereo CODEC with 1W Stereo Class D Speaker Drivers and Headphone Drivers for Portable Audio Applications

PDF	92 Pages

Scroll/Zoom	100%

制造商	WOLFSON [Wolfson Microelectronics plc]

网页	http://www.wolfsonmicro.com

标志

14 / 92 page

WM8960

Production Data

PD, August 2013, Rev 4.2

Test Conditions

DCVDD=1.8V, DBVDD=AVDD=SPKVDD1=SPKVDD2=3.3V, DGND=AGND=SPKGND1=SPKGND2=0V, TA=+25

oC, Slave

Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

ADCLRC/DACLRC propagation delay from BCLK falling edge

tDL

ADCDAT propagation delay from BCLK falling edge

tDDA

DACDAT setup time to BCLK rising edge

tDST

DACDAT hold time from BCLK rising edge

tDHT

AUDIO INTERFACE TIMING – SLAVE MODE

Figure 3 Digital Audio Data Timing – Slave Mode

Test Conditions

DCVDD=1.8V, DBVDD=AVDD=SPKVDD1=SPKVDD2=3.3V, DGND=AGND=SPKGND1=SPKGND2=0V, TA=+25

oC, Slave

Mode, fs=48kHz,

MCLK= 256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

tBCY

BCLK pulse width high

tBCH

BCLK pulse width low

tBCL

ADCLRC/DACLRC set-up time to BCLK rising edge

tLRSU

ADCLRC/DACLRC hold time from BCLK rising edge

tLRH

DACDAT hold time from BCLK rising edge

tDH

ADCDAT propagation delay from BCLK falling edge

tDD

DACDAT set-up time to BCLK rising edge

tDS

Note:

BCLK period should always be greater than or equal to MCLK period.

WM8960 数据表(PDF) 14 Page - Wolfson Microelectronics plc

WM8960 数据表(HTML) 14 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

数据表下载