WM8960 datasheet(57/92 Pages) WOLFSON

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Production Data

WM8960

PD, August 2013, Rev 4.2

SYSCLK can either be derived directly from MCLK, or generated from a PLL using MCLK as a

reference. The clock source is selected by CLKSEL. Many commonly-used audio sample rates can

be derived directly from MCLK, while the PLL provides additional flexibility.

The ADC and DAC sample rates are independently selectable, relative to SYSCLK, using ADCDIV

and DACDIV. In master mode, BCLK is also derived from SYSCLK via a programmable clock divide

(BCLKDIV).

When the ADCLRC/GPIO1 pin is configured as a GPIO, a clock derived from SYSCLK can be output

on this pin to provide clocking for other parts of the system. The frequency of this output clock is set

by OPCLKDIV.

A slow clock derived from SYSCLK is used to de-bounce the headphone detect function, and to set

the timeout period for volume updates when zero-cross functions are used. This clock is enabled by

TOEN and its frequency is set by TOCLKSEL.

The class D outputs require a clock, and this is also derived from SYSCLK via a programmable

divider (DCLKDIV) as shown in Figure 36. The class D switching clock should be set between 700kHz

and 800kHz.

The class D switching clock should not be disabled when the speaker outputs are active, as

this would prevent the speaker outputs from functioning. The class D switching clock

frequency should not be altered while the speaker outputs are active as this may generate an

audible click.

Table 39 shows the clocking and sample rate controls for MCLK input, BITCLK output (in master

mode), ADCs, DACs, class D outputs and GPIO clock output. Refer to Table 40 for example clocking

configurations.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4 (04h)

Clocking (1)

8:6

ADCDIV

[2:0]

000

ADC Sample rate divider (Also

determines ADCLRC in master mode)

000 = SYSCLK / (1.0 * 256)

001 = SYSCLK / (1.5 * 256)

010 = SYSCLK / (2 * 256)

011 = SYSCLK / (3 * 256)

100 = SYSCLK / (4 * 256)

101 = SYSCLK / (5.5 * 256)

110 = SYSCLK / (6 * 256)

111 = Reserved

5:3

DACDIV

[2:0]

000

DAC Sample rate divider (Also

determines DACLRC in master mode)

000 = SYSCLK / (1.0 * 256)

001 = SYSCLK / (1.5 * 256)

010 = SYSCLK / (2 * 256)

011 = SYSCLK / (3 * 256)

100 = SYSCLK / (4 * 256)

101 = SYSCLK / (5.5 * 256)

110 = SYSCLK / (6 * 256)

111 = Reserved

2:1

SYSCLKDIV

[1:0]

SYSCLK Pre-divider. Clock source

(MCLK or PLL output) will be divided by

this value to generate SYSCLK.

00 = Divide SYSCLK by 1

01 = Reserved

10 = Divide SYSCLK by 2

11 = Reserved

CLKSEL

SYSCLK selection

0 = SYSCLK derived from MCLK

1 = SYSCLK derived from PLL output

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