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WM8960 数据表(PDF) 62 Page - Wolfson Microelectronics plc |
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WM8960 数据表(HTML) 62 Page - Wolfson Microelectronics plc |
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62 / 92 page ![]() WM8960 Production Data w PD, August 2013, Rev 4.2 62 Device running in master mode with 24-bit data MCLK input at 12.288MHz ADC and DAC running at fs=48kHz BCLK running at 64fs Device running in slave mode with 24-bit data MCLK input at 12.288MHz ADC and DAC running at fs=48kHz BCLK supplied from host at 64fs in this example Device running in master mode with 24-bit data MCLK input at 11.2896MHz ADC running at fs=8.018kHz DAC running at fs=44.1kHz BCLK running at 64fs (relative to DAC sample rate, as DAC is operating at a higher sample rate than ADC) Device running in slave mode with 24-bit data MCLK input at 11.2896MHz ADC running at fs=8.018kHz DAC running at fs=44.1kHz BCLK supplied from host at 64fs in this example (relative to DAC sample rate, as DAC is operating at a higher sample rate than ADC) Device running in master mode with 24-bit data MCLK input at 12MHz PLL Enabled and configured for SYSCLK=11.2896MHz ADC running at fs=8.018kHz DAC running at fs=44.1kHz BCLK running at 64fs (relative to DAC sample rate, as DAC is operating at a higher sample rate than ADC) Class D clocks running at 705.6kHz Table 46 Example Clocking Schemes |
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