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WM8960 数据表(PDF) 75 Page - Wolfson Microelectronics plc |
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WM8960 数据表(HTML) 75 Page - Wolfson Microelectronics plc |
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75 / 92 page  Production Data WM8960 w PD, August 2013, Rev 4.2 75 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO Additional Control (2) 6 HPSWEN 0 Headphone Switch Enable 0 = Headphone switch disabled 1 = Headphone switch enabled Headphone Jack Detect 5 HPSWPOL 0 Headphone Switch Polarity 0 = HPDETECT high = headphone 1 = HPDETECT high = speaker Headphone Jack Detect 4 Reserved 3 TRIS 0 Tristates ADCDAT and switches ADCLRC, DACLRC and BCLK to inputs. 0 = ADCDAT is an output; ADCLRC, DACLRC and BCLK are inputs (slave mode) or outputs (master mode) 1 = ADCDAT is tristated; DACLRC and BCLK are inputs; ADCLRC is an input (when not configured as a GPIO) Audio Interface Control 2 LRCM 0 Selects disable mode for ADCLRC and DACLRC (Master mode) 0 = ADCLRC disabled when ADC (Left and Right) disabled; DACLRC disabled when DAC (Left and Right) disabled. 1 = ADCLRC and DACLRC disabled only when ADC (Left and Right) and DAC (Left and Right) are disabled. Audio Interface Control 1:0 0 Reserved R25 (19h) Power Mgmt (1) 8:7 VMIDSEL[1:0] 00 Vmid Divider Enable and Select 00 = Vmid disabled (for OFF mode) 01 = 2 x 50k divider enabled (for playback / record) 10 = 2 x 250k divider enabled (for low-power standby) 11 = 2 x 5k divider enabled (for fast start-up) Power Management 6 VREF 0 VREF (necessary for all other functions) 0 = Power down 1 = Power up Power Management 5 AINL 0 Analogue in PGA Left 0 = Power down 1 = Power up Power Management 4 AINR 0 Analogue in PGA Right 0 = Power down 1 = Power up Power Management 3 ADCL 0 ADC Left 0 = Power down 1 = Power up Power Management 2 ADCR 0 ADC Right 0 = Power down 1 = Power up Power Management 1 MICB 0 MICBIAS 0 = Power down 1 = Power up Power Management 0 DIGENB 0 Master Clock Disable 0 = Master clock enabled 1 = Master clock disabled Power Management R26 (1Ah) Power Mgmt (2) 8 DACL 0 DAC Left 0 = Power down 1 = Power up Power Management |
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