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WM8960 数据表(PDF) 74 Page - Wolfson Microelectronics plc |
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WM8960 数据表(HTML) 74 Page - Wolfson Microelectronics plc |
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74 / 92 page ![]() WM8960 Production Data w PD, August 2013, Rev 4.2 74 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 2:1 00 Reserved 0 NGAT 0 Noise gate function enable 0 = disable 1 = enable Automatic Level Control R21 (15h) Left ADC Volume 8 ADCVU N/A ADC Volume Update Writing a 1 to this bit will cause left and right ADC volumes to be updated (LADCVOL and RADCVOL) Analogue to Digital Converter 7:0 LADCVOL[7:0] 11000011 Left ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -97dB 0000 0010 = -96.5dB ... 0.5dB steps up to 1111 1111 = +30dB Analogue to Digital Converter R22 (16h) Right ADC Volume 8 ADCVU N/A ADC Volume Update Writing a 1 to this bit will cause left and right ADC volumes to be updated (LADCVOL and RADCVOL) Analogue to Digital Converter 7:0 RADCVOL[7:0] 11000011 Right ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -97dB 0000 0010 = -96.5dB ... 0.5dB steps up to 1111 1111 = +30dB Analogue to Digital Converter R23 (17h) Additional Control (1) 8 TSDEN 1 Thermal Shutdown Enable 0 = Thermal shutdown disabled 1 = Thermal shutdown enabled (TSENSEN must be enabled for this function to work) Thermal Shutdown 7:6 VSEL[1:0] 11 Analogue Bias Optimisation 00 = Reserved 01 = Increased bias current optimized for AVDD=2.7V 1X = Lowest bias current, optimized for AVDD=3.3V Power Management 5 0 Reserved 4 DMONOMIX 0 DAC Mono Mix 0 = Stereo 1 = Mono (Mono MIX output on enabled DACs) Output Signal Path 3:2 DATSEL[1:0] 00 ADC Data Output Select 00: left data = left ADC; right data =right ADC 01: left data = left ADC; right data = left ADC 10: left data = right ADC; right data =right ADC 11: left data = right ADC; right data = left ADC Analogue to Digital Converter 1 TOCLKSEL 0 Slow Clock Select (Used for volume update timeouts and for jack detect debounce) 0 = SYSCLK / 2 21 (Slower Response) 1 = SYSCLK / 2 19 (Faster Response) Volume Updates; Headphone Jack Detect 0 TOEN 0 Enables Slow Clock for Volume Update Timeout and Jack Detect Debounce 0 = Slow clock disabled 1 = Slow clock enabled Volume Updates; Headphone Jack Detect R24 (18h) 8:7 00 Reserved |
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