28F004SC datasheet(12/42 Pages) INTEL

12 / 42 page

BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY

PRELIMINARY

2.0

PRINCIPLES OF OPERATION

The byte-wide SmartVoltage FlashFile memories

include an on-chip WSM to manage block erase,

program, and lock-bit configuration functions. It

allows for: 100% TTL-level control inputs, fixed

power supplies during block erasure, program, and

lock-bit

configuration,

and

minimal

processor

overhead with RAM-like interface timings.

After initial device power-up or return from deep

power-down mode (see Bus

Operations),

the

device defaults to read array mode. Manipulation of

external memory control pins allow array read,

standby, and output disable operations.

Status

and

identifier

codes

can

accessed through the CUI independent of the VPP

voltage. High voltage on VPP enables successful

block erasure, program, and lock-bit configuration.

All functions associated with altering memory

contents—block

erase,

program,

lock-bit

configuration, status, and identifier codes—are

accessed via the CUI and verified through the

status register.

Commands are written using standard micro-

processor write timings. The CUI contents serve as

input to the WSM that controls block erase,

program, and lock-bit configuration operations. The

internal algorithms are regulated by the WSM,

including pulse repetition, internal verification, and

margining

data.

Addresses

and

data

are

internally latched during write cycles. Writing the

appropriate command outputs array data, accesses

the identifier codes, or outputs status register data.

Interface software that initiates and polls progress

of block erase, program, and lock-bit configuration

can be stored in any block. This code is copied to

and executed from system RAM during flash

memory updates. After successful completion,

reads are again possible via the Read Array

command. Block erase suspend allows system

software to suspend a block erase to read or write

data from any other block. Program suspend allows

system software to suspend a program to read data

from any other flash memory array location.

64-Kbyte Block

1FFFFF

1F0000

1EFFFF

1E0000

1DFFFF

1D0000

1CFFFF

1C0000

1BFFFF

1B0000

1AFFFF

1A0000

19FFFF

190000

18FFFF

180000

17FFFF

170000

16FFFF

160000

15FFFF

150000

14FFFF

140000

13FFFF

130000

12FFFF

120000

11FFFF

110000

10FFFF

100000

0FFFFF

0F0000

0EFFFF

0E0000

0DFFFF

0D0000

0CFFFF

0C0000

0BFFFF

0B0000

0AFFFF

0A0000

09FFFF

090000

08FFFF

080000

07FFFF

070000

06FFFF

060000

05FFFF

050000

04FFFF

040000

03FFFF

030000

02FFFF

020000

01FFFF

010000

00FFFF

000000

64-Kbyte Block

8-Mbit

16-Mbit

4-Mbit

Figure 5. Memory Map

28F004SC 数据表(PDF) 12 Page - Intel Corporation

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