28F004SC datasheet(37/42 Pages) INTEL

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BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY

PRELIMINARY

6.6

AC Characteristics—Write Operations(1,2)—Commercial Temperature

TA = 0°C to +70°C

5 V ± 5%,

5 V ± 10% VCC

Valid for All

Speeds



Versions

3.3 V ± 0.3 V,

2.7 V

−3.6 V VCC



Valid for All

Speeds

Unit

Sym

Parameter

Notes

Min

Max

Min

Max

tPHWL (tPHEL)

RP# High Recovery to WE# (CE#) Going

Low

1µs

tELWL (tWLEL)

CE# (WE#) Setup to WE# (CE#) Going

Low

0ns

tWP

Write Pulse Width

tDVWH (tDVEH)

Data Setup to WE# (CE#) Going High

tAVWH (tAVEH)

Address Setup to WE# (CE#) Going High

tWHEH (tEHWH)

CE# (WE#) Hold from WE# (CE#) High

0ns

tWHDX (tEHDX)

Data Hold from WE# (CE#) High

5ns

tWHAX (tEHAX)

Address Hold from WE# (CE#) High

5ns

tWPH

Write Pulse Width High

W10 tPHHWH (tPHHEH) RP# VHH Setup to WE# (CE#) Going High

3,8

100

W11 tVPWH (tVPEH)VPP Setup to WE# (CE#) Going High

3,8

100

W12 tWHGL (tEHGL)

Write Recovery before Read

0ns

W13 tWHRL (tEHRL)

WE# (CE#) High to RY/BY# Going Low

W14 tQVPH

RP# VHH Hold from Valid SRD, RY/BY#

High

3,5,8

0ns

W15 tQVVL

VPP Hold from Valid SRD, RY/BY# High

3,5,8

0ns

NOTES:

Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during

read-only operations. Refer to AC Characteristics for read-only operations.

A write operation can be initiated and terminated with either CE# or WE#.

Sampled, not 100% tested.

Refer to Table 4 for valid AIN and DIN for block erase, program, or lock-bit configuration.

VPP should be held at VPPH1/2/3 (and if necessary RP# should be held at VHH) until determination of block erase, program,

or lock-bit configuration success (SR.1/3/4/5 = 0).

See Ordering Information for device speeds (valid operational combinations).

Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high

(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. If CE# is driven low 10 ns before WE# going low,

WE# pulse width requirement decreases to tWP – 10 ns for 5 V VCC and tWP – 20 ns for 2.7 V and 3.3 V VCC writes.

Block erase, program, and lock-bit configuration with VCC < 3.0 V should not be attempted.

Write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low

(whichever goes low last). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.

28F004SC 数据表(PDF) 37 Page - Intel Corporation

28F004SC 数据表(HTML) 37 Page - Intel Corporation

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