28F004SC datasheet(32/42 Pages) INTEL

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BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY

PRELIMINARY

6.4

DC Characteristics—Commercial Temperature(Continued)

2.7 V VCC 3.3 V VCC 5 V VCC

Test

Sym

Parameter

Notes Min Max Min Max Min Max Unit

Conditions

VIL

Input Low Voltage

–0.5 0.8 –0.5 0.8 –0.5 0.8

VIH

Input High Voltage

2.0 VCC

+ 0.5

2.0 VCC

+ 0.5

2.0 VCC

+ 0.5

VOL

Output Low Voltage

3,7

0.4

0.45

VCC = VCC Min

IOL = 2 mA (2.7V, 3.3V)

5.8 mA (5V)

VOH1 Output High Voltage (TTL)

3,7

2.4

VCC = VCC Min

IOH = –2.5 mA

VOH2 Output High Voltage

(CMOS)

3,7

0.85

VCC

0.85

VCC

0.85

VCC

VVCC = VCC Min

IOH = –2.5 mA

VCC

–0.4

VCC

–0.4

VCC

–0.4

VVCC = VCC Min

IOH = –100 µA

VPPLK VPP Lockout Voltage

4,7

1.5

VPPH1 VPP Voltage



3.0

3.6



VPPH2 VPP Voltage



4.5

5.5

4.5

5.5

VPPH3 VPP Voltage

 11.4 12.6 11.4 12.6 V

VLKO VCC Lockout Voltage

2.0

VHH

RP# Unlock Voltage

8,9

 11.4 12.6 11.4 12.6 V Set Master Lock-Bit

Override Lock-Bit

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA = +25

°C. These currents are

valid for all product versions (packages and speeds).

2. ICCWS and ICCES are specified with the device de-selected. If read or written while in erase suspend mode, the device’s

current is the sum of ICCWS or ICCES and ICCR or ICCW.

3. Includes RY/BY#.

4. Block erases, programs, and lock-bit configurations are inhibited when VPP

≤ VPPLK, and not guaranteed in the range

between VPPLK (max) and VPPH1 (min), between VPPH1 (max) and VPPH2 (min), between VPPH2 (max) and VPPH3 (min), and

above VPPH3 (max).

5. Automatic Power Savings (APS) reduces typical ICCR to 1 mA at 5 V and 3 mA at 2.7 V and 3.3 V VCC in static operation.

6. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL inputs are either VIL or VIH.

7. Sampled, not 100% tested.

8. Master lock-bit set operations are inhibited when RP# = VIH. Block lock-bit configuration operations are inhibited when the

master lock-bit is set and RP# = VIH. Block erases and programs are inhibited when the corresponding block-lock bit is set

and RP# = VIH. Block erase, program, and lock-bit configuration operations are not guaranteed and should not be

attempted with VIH < RP# < VHH.

9. RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours.

28F004SC 数据表(PDF) 32 Page - Intel Corporation

28F004SC 数据表(HTML) 32 Page - Intel Corporation

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28F004SC 数据表(PDF) 32 Page - Intel Corporation

28F004SC 数据表(HTML) 32 Page - Intel Corporation

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