28F004SC datasheet(27/42 Pages) INTEL

27 / 42 page

BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY

PRELIMINARY

SR.7 =

Start

Write 60H

Write D0H

Full Status

Check if Desired

Clear Block Lock-Bits

Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Read Status

Range Error

Command Sequence

Error

SR.3 =

SR.5 =

SR.4,5 =

Clear Block Lock-Bits

Error

Bus

Operation

Command

Comments

Standby

Check SR.4,5

Both 1 = Command Sequence Error

Standby

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status

If error is detected, clear the Status Register before attempting

retry or other error recovery.

Check SR.5

1 = Clear Block Lock-Bits Error

Standby

Bus

Operation

Command

Comments

Write

Clear Block

Lock-Bits Setup

Read

Data = 60H

Addr = X

Check SR.7

1 = WSM Ready

0 = WSM Busy

Write FFH after the Clear Block Lock-Bits operation to place device

to read array mode.

Status Register Data

Standby

Clear Block

Lock-Bits Confirm

Data = D0H

Addr = X

Clear Block Lock-Bits

Successful

Standby

Device Protect Error

SR.1=

Check SR.3

1 = V

Error Detect

Check SR.1

1 = Device Protect Detect

RP# = V , Master Lock-Bit Is Set

Figure 12. Clear Block Lock-Bits Flowchart

28F004SC 数据表(PDF) 27 Page - Intel Corporation

28F004SC 数据表(HTML) 27 Page - Intel Corporation

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28F004SC 数据表(PDF) 27 Page - Intel Corporation

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