28F004SC datasheet(7/42 Pages) INTEL

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BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY

PRELIMINARY

4-Mbit: A - A

8-Mbit: A - A

16-Mbit: A - A

020

Input

Buffer

Output

Buffer

Identifier

Status

Command

I/O Logic

Data

Comparator

Input

Buffer

Address

Latch

Address

Counter

Decoder

Y Gating

4-Mbit: Eight

8-Mbit: Sixteen

16-Mbit: Thirty-Two

64-Kbyte Blocks

Write State

Machine

Program/Erase

Voltage Switch

CE#

WE#

OE#

RP#

RY/BY#

GND

DQ - DQ

VCC

Figure 1. Block Diagram

Table 2. Pin Descriptions

Sym

Type

Name and Function

A0–A20

INPUT

ADDRESS INPUTS: Inputs for addresses during read and write operations.

Addresses are internally latched during a write cycle.

4 Mbit

→ A

0–A18

8 Mbit

→ A

0–A19

16 Mbit

→ A

0–A20

DQ0–DQ7

INPUT/

OUTPUT

DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles;

outputs data during memory array, status register, and identifier code read cycles.

Data pins float to high-impedance when the chip is deselected or outputs are

disabled. Data is internally latched during a write cycle.

CE#

INPUT

CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and

sense amplifiers. CE#-high deselects the device and reduces power consumption to

standby levels.

RP#

INPUT

RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations

which provides data protection during power transitions, puts the device in deep

power-down mode, and resets internal automation. RP#-high enables normal

operation. Exit from deep power-down sets the device to read array mode.

RP# at VHH enables setting of the master lock-bit and enables configuration of block

lock-bits when the master lock-bit is set. RP# = VHH overrides block lock-bits,

thereby enabling block erase and program operations to locked memory blocks.

Block erase, program, or lock-bit configuration with VIH < RP# < VHH produce

spurious results and should not be attempted.

OE#

INPUT

OUTPUT ENABLE: Gates the device’s outputs during a read cycle.

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