BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY

E

16

PRELIMINARY

Bus Cycles

First Bus Cycle

Second Bus Cycle

Command

Req’d.

Notes

Read Array/Reset

1

Write

X

FFH

Read Identifier Codes

≥ 2

4

Write

X

90H

Read

IA

ID

Read Status Register

2

Write

X

70H

Read

X

SRD

Clear Status Register

1

Write

X

50H

Block Erase

2

5

Write

BA

20H

Write

BA

D0H

Program

2

5,6

Write

PA

40H

or

10H

Write

PA

PD

Block Erase and Program

Suspend

1

5

Write

X

B0H

Block Erase and Program

Resume

1

5

Write

X

D0H

Set Block Lock-Bit

2

7

Write

BA

60H

Write

BA

01H

Set Master Lock-Bit

2

7

Write

X

60H

Write

X

F1H

Clear Block Lock-Bits

2

8

Write

X

60H

Write

X

D0H

NOTES:

1. Bus operations are defined in Table 3.

2. X = Any valid address within the device.

IA = Identifier Code Address: see Figure 6.

BA = Address within the block being erased or locked.

PA = Address of memory location to be programmed.

3. SRD = Data read from status register. See Table 7 for a description of the status register bits.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).

ID = Data read from identifier codes.

4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock

codes. See Section 4.2 for read identifier code data.

6. Either 40H or 10H are recognized by the WSM as the program setup.

9. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.