28F004SC datasheet(18/42 Pages) INTEL

18 / 42 page

BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY

PRELIMINARY

When the block erase is complete, status register

bit SR.5 should be checked. If a block erase error is

detected, the status register should be cleared

before system software attempts corrective actions.

The CUI remains in read status register mode until

a new command is issued.

This

two-step

command

sequence

set-up

followed by execution ensures that block contents

are not accidentally erased. An invalid Block Erase

command sequence will result in both status

reliable

block

erasure

can

only

occur

when

VCC = VCC2/3 and VPP = VPPH1/2/3. In the absence of

this high voltage, block contents are protected

against erasure. If block erase is attempted while

VPP ≤ VPPLK, SR.3 and SR.5 will be set to “1.”

Successful

block

erase

requires

that

the

corresponding block lock-bit be cleared or, if set,

that RP# = VHH. If block erase is attempted when

the

corresponding

block

lock-bit

set

and

RP# = VIH, the block erase will fail, and SR.1 and

SR.5 will be set to “1.” Block erase operations with

VIH < RP# < VHH produce spurious results and

should not be attempted.

4.6

Program Command

Program is executed by a two-cycle command

sequence.

Program

setup

(standard

40H

alternate 10H) is written, followed by a second write

that specifies the address and data (latched on the

rising edge of WE#). The WSM then takes over,

controlling the program and write verify algorithms

internally. After the program sequence is written,

the device automatically outputs status register

data when read (see Figure 8). The CPU can detect

the completion of the program event by analyzing

the RY/BY# pin or status register bit SR.7.

When program is complete, status register bit SR.4

should be checked. If program error is detected, the

status register should be cleared. The internal WSM

verify only detects errors for “1”s that do not

successfully write to “0”s. The CUI remains in read

status register mode until it receives another

command.

Reliable programs only occurs when VCC = VCC2/3

and VPP = VPPH1/2/3. In the absence of this high

voltage, memory contents are protected against

programs.

program

attempted

while

VPP

≤ VPPLK, the operation will fail, and status

Successful

program

also

requires

that

the

corresponding block lock-bit be cleared or, if set,

that RP# = VHH. If program is attempted when the

corresponding block lock-bit is set and RP# = VIH,

program will fail, and SR.1 and SR.4 will be set to

“1.” Program operations with VIH < RP# < VHH

produce spurious

results

and

should

not

attempted.

4.7

Block Erase Suspend

Command

The

Block

Erase

Suspend

command

allows

block-erase interruption to read or write data in

another block of memory. Once the block erase

process starts, writing the Block Erase Suspend

command requests that the WSM suspend the

block erase sequence at a predetermined point in

the algorithm. The device outputs status register

data when read after the Block Erase Suspend

command is written. Polling status register bits

SR.7 and SR.6 can determine when the block erase

operation has been suspended (both will be set to

“1”).

RY/BY#

will

also

transition

VOH.

Specification

tWHRH2 defines the block erase

suspend latency.

At this point, a Read Array command can be written

to read data from blocks other than that which is

suspended. A Program command sequence can

also be issued during erase suspend to program

data in other blocks. Using the Program Suspend

command (see Section 4.8), a program operation

can also be suspended. During a program operation

with block erase suspended, status register bit

SR.7 will return to “0” and the RY/BY# output will

transition to VOL. However, SR.6 will remain “1” to

indicate block erase suspend status.

The only other valid commands while block erase is

suspended are Read Status Register and Block

Erase Resume. After a Block Erase Resume

command is written to the flash memory, the WSM

will continue the block erase process. Status

and RY/BY# will return to VOL. After the Erase

Resume

command

written,

the

device

automatically outputs status register data when

read (see Figure 9). VPP must remain at VPPH1/2/3

(the same VPP level used for block erase) while

block erase is suspended. RP# must also remain at

VIH or VHH (the same RP# level used for block

erase). Block erase cannot resume until program

operations initiated during block erase suspend

have completed.

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