28F004SC datasheet(21/42 Pages) INTEL

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BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY

PRELIMINARY

Table 7. Status Register Definition

WSMS

ESS

ECLBS

PSLBS

VPPS

PSS

DPS

654

321

NOTES:

SR.7 = WRITE STATE MACHINE STATUS

1 = Ready

0 = Busy

Check RY/BY# or SR.7 to determine block erase,

program, or lock-bit configuration completion.

SR.6–0 are invalid while SR.7 = “0.”

SR.6 = ERASE SUSPEND STATUS

1 = Block Erase Suspended

0 = Block Erase in Progress/Completed

SR.5 = ERASE AND CLEAR LOCK-BITS

STATUS

1 = Error in Block Erasure or Clear Lock-Bits

0 = Successful Block Erase or Clear Lock-Bits

If both SR.5 and SR.4 are “1”s after a block erase or

lock-bit configuration attempt, an improper

command sequence was entered.

SR.4 = PROGRAM AND SET LOCK-BIT

STATUS

1 = Error in Program or Set Master/Block

Lock-Bit

0 = Successful Program or Set Master/Block

Lock-Bit

SR.3 = VPP STATUS

1 = VPP Low Detect, Operation Abort

0 = VPP OK

SR.3 does not provide a continuous indication of

VPP level. The WSM interrogates and indicates the

VPP level only after a block erase, program, or lock-

bit configuration operation. SR.3 is not guaranteed

to reports accurate feedback only when VPP

≠

VPPH1/2/3.

SR.2 = PROGRAM SUSPEND STATUS

1 = Program Suspended

0 = Program in Progress/Completed

SR.1 = DEVICE PROTECT STATUS

1 = Master Lock-Bit, Block Lock-Bit and/or

RP# Lock Detected, Operation Abort

0 = Unlock

SR.1 does not provide a continuous indication of

master and block lock-bit values. The WSM

interrogates the master lock-bit, block lock-bit, and

RP# only after a block erase, program, or lock-bit

configuration operation. It informs the system,

depending on the attempted operation, if the block

lock-bit is set, master lock-bit is set, and/or

RP#

≠ VHH.

SR.0 = RESERVED FOR FUTURE

ENHANCEMENTS

SR.0 is reserved for future use and should be

masked out when polling the status register.

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