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28F004SC 数据表(PDF) 34 Page - Intel Corporation |
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28F004SC 数据表(HTML) 34 Page - Intel Corporation |
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34 / 42 page ![]() BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY E 34 PRELIMINARY IH V IL V RP# (P) IH V IL V RY/BY# (R) P1 P2 Figure 17. AC Waveform for Reset Operation Table 8. Reset Specifications 2.7 V VCC 3.3 V VCC 5 V VCC # Sym Parameter Notes Min Max Min Max Min Max Unit P1 tPLPH RP# Pulse Low Time (If RP# is tied to VCC, this specification is not applicable) 100 100 100 ns P2 tPLRH RP# Low to Reset during Block Erase, Program, or Lock-Bit Configuration 2,3 20 12 µs NOTES: 1. These specifications are valid for all product versions (packages and speeds). 2. If RP# is asserted when the WSM is not busy (RY/BY# = “1”), the reset will complete within 100 ns. 3. A reset time, tPHQV, is required from the latter of RY/BY# or RP# going high until outputs are valid. |
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