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ST9 USER GUIDE

3.5 DMA CONTROLLER

3.5.1 Overview

One of the most important advantages of the ST9 is its ability to handle input/output data flows

without using core instruction cycles. This is made possible by the built-in DMA controller.

Once properly initialized, it allows peripherals to exchange data either with memory or the reg-

ister file, with no more use of the core resources than the stolen memory cycles strictly needed

to transfer the data.

To see how much faster DMA is than the simplest interrupt service routine, let us compare the

execution times.

Let us assume that the data comes from the serial port. The simplest interrupt routine is the

following:

GetOneByte:; interrupt latency:

22 cycles

push

PPR

; save current page

pushw

rr0

; save rr0

spp

#SCI_PG

; change register page

ldw

rr0, POINTER

; get pointer

(rr0)+, S_RXBR

; move data

ldw

POINTER, rr0

; store pointer

popw

rr0

; restore rr0

pop

PPR

; restore current page

iret

; return

; -------------------------------------------

; Total:

116

With an internal clock of 24 MHz, this corresponds to an execution time of 4.8364 µs. In con-

trast, the DMA cycle time for the transfer of one byte from a register to a register file takes only

8 cycles (16 cycles to the memory), that is 0.33 µs. The DMA feature saves you from using

valuable core processing power for simple tasks like storing an input byte to memory. For ex-

ample, if a continuous flow of data is input at 19200 bits per second, the interrupt service rou-

tine would consume 1.11% of the total cycles of the core, as compared to the 0.0767% with

the DMA solution. Since the DMA is built-in and works with most of the peripherals, it is a good

idea to use it even for slow transfers.

The DMA uses the Segment mechanism to address 64 Kbytes along the linear 4 MBytes. See

Section 3.1.7 for more details.

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