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ST9 数据表(PDF) 69 Page - STMicroelectronics |
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ST9 数据表(HTML) 69 Page - STMicroelectronics |
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69 / 146 page  69/146 ST9 USER GUIDE reload it with its initial value. You select these modes using three bits in the WDT Control Reg- ister, as follows: 4.3.1.1 Event Counter Mode The counter value is decremented at each falling edge on the WDTIN pin if ST_SP is high (bit 7 of WDTCR). Figure 28 . Timer in Event Counter Mode 4.3.1.2 Gated Input Mode The counter value is decremented by WDTCLK (INTCLK / 4) if the WDTIN pin and ST_SP are high. Figure 29 . Timer in Gated Input Mode INEN INMD1 INMD2 Mode 1 0 0 Event counter mode 1 0 1 Gated mode 1 1 1 Retriggerable input mode 1 1 0 Triggerable input mode 0 X X Input section disabled. Internal clock selected. WDTIN Pin ST_SP Counter Value WDTIN Pin ST_SP Counter Value |
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