ST9 datasheet(47/146 Pages) STMICROELECTRONICS

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ST9 USER GUIDE

3.4.2 Interrupt Priorities

In any microprocessor-based system, there is a trade-off between the computational power of

the main program and the interrupt latency time. Expressed simply, the less the main program

is disturbed, the sooner it finishes its job. On the other hand, we often need to serve interrupt

requests generated by the peripherals as quickly as possible. Since this is a trade-off, we

need to find a compromise that gives both enough power to the main program while still

keeping it as responsive as possible to interrupts. It is likely that we will need to modify this

compromise according to the current status of the program.

If we define that some interrupt requests are more urgent than others, we can define a priority

or a hierarchy of interrupt requests. The main program itself, if given a priority level, should be

considered as having the lowest priority (except sometimes when interrupts are undesirable).

In most cases, when the main program is running, it can be interrupted by any interrupt re-

quest. But once a request is being served, it most likely needs to continue undisturbed, unless

a request from a higher priority level occurs. Then, the higher priority request is served until

completion. The service routine then returns to the lower priority interrupt service routine, that

terminates and eventually returns to the main program. In the ST9, this behavior is called

Nested Mode.

Other types of behavior may be required depending of the kind of processing. For this, the

ST9 interrupt system has two Boolean parameters to select the way interrupts are handled,

which allow four basic choices.

The priority mechanism is driven by the Current Priority Level parameter. At a given time, the

part of the program being executed runs under a certain level. You can change this CPL by

writing a different value in the core’s Central Interrupt Control Register (CICR). You can assign

Priority Level (PL) to each interrupt source. At initialisation time, this value is written in one of

the control registers specific to the corresponding peripheral.

Note:

The PL is a three-bit word that ranges from 0 to 7. Note that 0 stands for a high priority and 7

for a low priority. These bits belong to one of the configuration registers of each peripheral.

When a peripheral requests an interrupt, the built-in interrupt controller compares the priority

level of the interrupt request to the Current Priority Level. The interrupt is only acknowledged

if its priority level value is strictly less than (higher priority) than the Current Priority Level

value. This allows you to filter out interrupt requests according to their degree of importance or

of urgency according to the current activity of the program. The Non-Maskable Interrupt input

(NMI) is hard wired with a higher priority than any level, and thus is acknowledged immediately

in all circumstances.

The ST9 offers two modes for managing interrupt priorities:

– Concurrent Mode

– Nested Mode

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