ST9 datasheet(100/146 Pages) STMICROELECTRONICS

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ST9 USER GUIDE

isters e.g AD_D0R is made up of AD_D0LR (For lower 2 bits of 10 bits result) and AD_D0HR

(For upper 8 bits of 10 bits result).

The end of conversion sets the ECV bit in the AD_ICR register, and can trigger an interrupt re-

quest, if the ECI bit (mask of the end of conversion interrupt request) of the Interrupt Control

Notes

The internal interrupt controller does not automatically reset the ECV bit. It must be reset by the

interrupt service routine prior to returning from interrupt. Failure to do this would cause the in-

terrupt to loop endlessly.

As mentioned in

Section 4.2 on parallel ports, you must configure the corresponding pins to

alternate function both to reduce loading on the analog source and to avoid excessive dissipa-

tion in the pin's input buffer. For the same reason, it is advised to keep this I/O configuration if

an analog voltage is present on the pin, even if it is not being converted at this time.

4.7.2 Analog Watchdog

A special feature of this peripheral is the so-called Analog Watchdog. If enabled, the values of

Channel A or both Channel A and Channel B are each compared after each conversion with

a pair of upper and lower thresholds stored in registers AD_LTAR (AD_LTAHR,AD_LTALR),

AD_UTAR(AD_UTAHR,AD_UTALR) for Channel A, and AD_LTBR(AD_LTBHR,AD_LTBLR),

AD_UTBR(AD_UTBHR,AD_UTBLR) for Channel B. Channel A and Channel B are selected

by CC[3:0] bits in control register AD_CLR1.

If the value is outside the threshold values, the AWD bit of the AD_ICR register is set. This can

trigger an interrupt request if the AWDI bit of the same register is set. To know which of the

four thresholds has been exceeded, the Compare Result Register (CRR) has four bits with

one each corresponding to one of these thresholds. The appropriate bit is set when the

threshold has been exceeded.

Notes:

The AWD bit, like the ECV bit, is not automatically reset by the internal interrupt controller. Thus

it must be reset by the interrupt service routine prior to returning from interrupt. Failure to do this

would cause the interrupt to loop endlessly.

To permit power saving in applications where energy conservation is important, you can power

the ADC on and off so that it only consumes power when used. However when you switch it on,

after a delay of 10 µs first conversion starts. The reset condition is off.

4.7.3 Interrupt Vectoring

Two vectors are dedicated to the ADC: the end of conversion vector and the analog watchdog

vector. This allows these two events to be serviced by two different routines. The vectors used

depends on the state of the W1 bit in the AD_IVR register. This bit is set or reset according to

the source of the interrupt.

However, it may occur that both interrupts are generated simultaneously. In that case, analog

watchdog has Priority over End of Conversion request.

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