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ST9 USER GUIDE

DAPR indicates whether the memory segment is pointed by DMASR or ISR (see Section

3.1.7). The DMA address and the DMA transaction counter are not necessarily consecutive.

3.5.2.3 Transfer Termination

A burst terminates when the count of transfers reaches a predefined value. To set this up, you

set a counter register in the register file that holds the count of transfers to execute at the start

of a burst. Each transfer decrements it, and the DMA mechanism is stopped when the counter

reaches zero.

The way DMA controller terminates the transfer differs from one peripheral to another, but typ-

ically it consists of resetting the bit in the configuration register that tells the peripheral to issue

DMA requests instead of interrupt requests. Then, on the last transfer, when the transfer

counter reaches zero, it toggles the DMA/Interrupt request bit so that the peripheral issues an

interrupt request again. If this request is unmasked, you should vector it to an interrupt service

routine that handles the DMA termination.

To summarise:

For register transfers, the DCPR of the peripheral points to a user-defined pair of registers that

holds the address and the count. Register DAPR is unused. For memory transfers, the DAPR

points to the user-defined register pair that holds the address. The DCPR register points to the

user-defined register pair that holds the count.

Some peripherals, such as the Multifunction Timer, even have a double pair of DAPR/DCPR

registers. Only one pair is used at a time. In so-called Swap Mode, this allows the timer to use

one data buffer for output and another buffer for input. The pair of registers used is automati-

cally changed when one transfer burst terminates, allowing a continuous data flow between

the program and the peripheral, with minimum data handling overhead.

In addition, the MFT has 16-bit registers. Transfers imply two byte transfers for each register.

This is ensured by a mechanism that gives the DMA the highest priority as soon as the first

byte is transferring. This guarantees that the second byte will also be transferred in the

shortest delay, even if other DMA requests become pending while the transfer is in progress.

ST9 数据表(PDF) 58 Page - STMicroelectronics