ST9 datasheet(78/146 Pages) STMICROELECTRONICS

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ST9 USER GUIDE

Figure 36

. MFT Interrupt Vector Register

The Interrupt and DMA Mask Register individually enable and disable the various interrupt

and DMA sources.

Figure 37

. MFT Interrupt and DMA Mask Register

The upper five bits of the Interrupt and DMA Control Register indicate the status of the inter-

rupts and the DMA blocks. The lower three bits set the Interrupt and DMA priority level.

IVR (R242 page 9 MFT0) (R246 page 9 MFT1)

Interrupt Vector Register

Not used

MSB of the vector

by software inside the

interrupt vector table

address table, fixed

LSB of the vector address table, fixed by hardware

Overflow/underflow event interrupts

Not Available

Capture event interrupts

Compare event interrupts

Interrupt Source

V1 V0

W1 W0 D0

IDMR (R255)

Interrupt / DMA Mask Register

OVF Interrupt Mask

Compare 1 Interrupt Mask

Compare 0 Interrupt Mask

Compare 0 DMA Mask

Capture 1 Interrupt Mask

Capture 0 Interrupt Mask

Capture 0 DMA Mask

Global Timer Interrupt Enable

GTIEN CP0D CP0I CP1I CM0D CM0I CM1I 0UI

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