ST9 datasheet(95/146 Pages) STMICROELECTRONICS

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ST9 USER GUIDE

– Set the transmit transaction counter to the number of characters to be transmitted minus one

(not the TDCPR, which is also only set once at initialisation, and points permanently to the

transmit transaction counter).

– Set the TXD bit of the IDPR register. This bit enables the Transmitter holding register empty

flag (TXHEM bit of register ISR) to trigger a DMA transfer when the last character is sent.

When TXD is reset, the holding register empty flag would trigger an interrupt instead.

– Load the Transmit Buffer Register (TXBR) with the first character to be sent. This starts the

DMA process as soon as this character is transmitted.

– Clear the Transmitter holding register empty flag (TXHEM bit of register ISR) and the Trans-

mitter buffer register empty flag (TXSEM bit of register ISR) to prevent DMA transfer from

starting before the first character is fully transmitted.

– Enable the end of DMA interrupt by setting the Transmitter Data Interrupt Mask (TXDI bit of

The DMA is now started and will stop when the transaction counter reaches zero.

Note:

The transmit address register is initialized with the address of the second word and the transmit

transaction counter is initialized to the number of characters to be transmitted minus one, be-

cause the DMA transfer begins when the first word is transmitted (a write in the Transmit Holding

4.6.1.2.2 Receiver Side

The receiver side is a little more complicated as two kinds of events can occur during recep-

tion:

– There can be transmission errors that must be handled.

– A break is received or a character match event can occur.

The receiver is set in a ready for DMA condition by the initialisation code.

Reception normally finishes when the DMA transaction counter has reached zero. But this is

not necessarily the way one wants to use the serial input, since it implies that the number of

characters to be received must be known before the transfer starts. In most cases, character-

type messages have a variable length.

In this application, the transaction counter is not expected to reach zero, since the size of the

buffer assigned for reception exceeds the longest message defined in the specification. Thus,

if the transaction counter reaches zero this is in fact an overflow condition. In this case, the

contents of the buffer are discarded and a new reception is initiated. In both cases, the steps

to perform an End of Block are:

– Reset the Receiver End of Block (RXEOB bit of register IMR) to remove the interrupt request.

– Use the received characters, if required.

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