ST9 datasheet(124/146 Pages) STMICROELECTRONICS

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ST9 USER GUIDE

230

CICR

Enables the MFTs,

enables the inter-

rupts, selects the ar-

bitration mode

(concurrent mode or

nested mode), and

the priority level of the

main program.

The GCEN bit of this register enables all the MFTs at

once. It may also be set once the MFTs are all initial-

ised, if it is desired that they be synchronised or that

they do not start before the remainder of the program

is ready.

The IEN bit enables all the interrupts at once. Again,

it may be set now, or only when the remainder of the

program is ready to process them.

The IAM bit selects either Concurrent Mode or Nested

Mode. It is better to do it now.

The three bits, CPL2 to CPL0, set the level of the

main program. Its value depends on the structure of

the program. Typically, it is set to 7, since the main

program is likely to be the low-priority process. See

the paragraph on interrupts in

Section 3.4.

234

PPR

Sets the page

number for the paged

zero.

This register will probably be changed several times

during the execution of the program. It is first set now,

if the WCR needs to be initialised.

250

page 0

WDTPR

Prescaler register of

the WatchDog Timer.

If the WDT is used as a watchdog(†), it should be ini-

tialised before the WDGEN bit is cleared in the WCR

it right now. See note for values.

248-249

page 0

WDTHR+W

DTLR

Reload register of the

WDT.

Same note as above.

251

page 0

WDTCR

Mode control register

of the WDT.

Same note as above.

252

page 0

WCR

Starts (or not) the

watchdog function of

the WDT, selects the

wait states for exter-

nal memory access

independently for up-

per and lower memo-

ries.

If you use the Watchdog function, first initialise the

Watchdog Timer. You can start it later using the

WDGEN bit of this register, but no protection is on be-

fore this time.

The external memory access is set by default to the

maximum number of wait states to allow the program

to start. You should reduce it to the exact number re-

quired by the type of memory to achieve maximum

performance.

(*)

Some register functions may not be mentioned if not relevant for the initialisation.

(†) Device Datasheet; §9

Number

Name

Function(*)

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