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STM32F756VG 数据表(PDF) 147 Page - STMicroelectronics |
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STM32F756VG 数据表(HTML) 147 Page - STMicroelectronics |
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147 / 228 page  DocID027589 Rev 4 147/228 STM32F756xx Electrical characteristics 196 fADC ADC clock frequency VDDA = 1.7(1) to 2.4 V 0.6 15 18 MHz VDDA = 2.4 to 3.6 V 0.6 30 36 MHz fTRIG(2) External trigger frequency fADC = 30 MHz, 12-bit resolution - - 1764 kHz -- - 17 1/fADC VAIN Conversion voltage range(3) - 0 (VSSA or VREF- tied to ground) -VREF+ V RAIN(2) External input impedance See Equation 1 for details -- 50 k Ω RADC(2)(4) Sampling switch resistance - - - 6 k Ω CADC(2) Internal sample and hold capacitor -- 4 7 pF tlat(2) Injection trigger conversion latency fADC = 30 MHz - - 0.100 µs -- 3(5) 1/fADC tlatr(2) Regular trigger conversion latency fADC = 30 MHz - - 0.067 µs -- 2(5) 1/fADC tS(2) Sampling time fADC = 30 MHz 0.100 - 16 µs - 3 - 480 1/fADC tSTAB(2) Power-up time - - 2 3 µs tCONV(2) Total conversion time (including sampling time) fADC = 30 MHz 12-bit resolution 0.50 - 16.40 µs fADC = 30 MHz 10-bit resolution 0.43 - 16.34 µs fADC = 30 MHz 8-bit resolution 0.37 - 16.27 µs fADC = 30 MHz 6-bit resolution 0.30 - 16.20 µs 9 to 492 (tS for sampling +n-bit resolution for successive approximation) 1/fADC fS(2) Sampling rate (fADC = 30 MHz, and tS = 3 ADC cycles) 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.75 Msps 12-bit resolution Interleave Triple ADC mode - - 6 Msps Table 62. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit |
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