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LSM6DS33 数据表(PDF) 61 Page - STMicroelectronics |
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LSM6DS33 数据表(HTML) 61 Page - STMicroelectronics |
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61 / 77 page  DocID027423 Rev 4 61/77 LSM6DS33 Register description 77 9.41 FIFO_STATUS4 (3Dh) FIFO status control register (r). For a proper reading of the register, it is recommended to set the BDU bit in CTRL3_C (12h) to 1. Table 111. FIFO_STATUS4 register Table 112. FIFO_STATUS4 register description 9.42 FIFO_DATA_OUT_L (3Eh) FIFO data output register (r). For a proper reading of the register, it is recommended to set the BDU bit in CTRL3_C (12h) to 1. 9.43 FIFO_DATA_OUT_H (3Fh) FIFO data output register (r). For a proper reading of the register, it is recommended to set the BDU bit in CTRL3_C (12h) to 1. 0(1) 1. This bit must be set to ‘0’ for the correct operation of the device. 0(1) 0(1) 0(1) 0(1) 0(1) FIFO_ PATTERN_9 FIFO_ PATTERN_8 FIFO_ PATTERN_[9:8] Word of recursive pattern read at the next reading. Table 113. FIFO_DATA_OUT_L register DATA_ OUT_ FIFO_L_7 DATA_ OUT_ FIFO_L_6 DATA_ OUT_ FIFO_L_5 DATA_ OUT_ FIFO_L_4 DATA_ OUT_ FIFO_L_3 DATA_ OUT_ FIFO_L_2 DATA_ OUT_ FIFO_L_1 DATA_ OUT_ FIFO_L_0 Table 114. FIFO_DATA_OUT_L register description DATA_OUT_FIFO_L_[7:0] FIFO data output (first byte) Table 115. FIFO_DATA_OUT_H register DATA_ OUT_ FIFO_H_7 DATA_ OUT_ FIFO_H_6 DATA_ OUT_ FIFO_H_5 DATA_ OUT_ FIFO_H_4 DATA_ OUT_ FIFO_H_3 DATA_ OUT_ FIFO_H_2 DATA_ OUT_ FIFO_H_1 DATA_ OUT_ FIFO_H_0 Table 116. FIFO_DATA_OUT_H register description DATA_OUT_FIFO_H_[7:0] FIFO data output (second byte) |
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