LSM6DS33 datasheet(49/77 Pages) STMICROELECTRONICS

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LSM6DS33

9.13

CTRL3_C (12h)

Control register 3 (r/w).

Table 49. CTRL3_C register

BOOT

BDU

H_LACTIVE

PP_OD

SIM

IF_INC

BLE

SW_RESET

Table 50. CTRL3_C register description

BOOT

Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content(1))

1. Boot request is executed as soon as internal oscillator is turned on. It is possible to set bit while in power-

down mode, in this case it will be served at the next normal mode or sleep mode.

BDU

Block Data Update. Default value: 0

(0: continuous update; 1: output registers not updated until MSB and LSB have

been read)

H_LACTIVE

Interrupt activation level. Default value: 0

(0: interrupt output pads active high; 1: interrupt output pads active low)

PP_OD

Push-pull/open-drain selection on INT1 and INT2 pads. Default value: 0

(0: push-pull mode; 1: open-drain mode)

SIM

SPI Serial Interface Mode selection. Default value: 0

(0: 4-wire interface; 1: 3-wire interface).

IF_INC

serial interface (I2C or SPI). Default value: 1

(0: disabled; 1: enabled)

BLE

Big/Little Endian Data selection. Default value 0

(0: data LSB @ lower address; 1: data MSB @ lower address)

SW_RESET

Software reset. Default value: 0

(0: normal mode; 1: reset device)

This bit is cleared by hardware after next flash boot.

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