LAN9211 datasheet(11/147 Pages) SMSC

11 / 147 page

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

SMSC LAN9211

Revision 2.9 (03-01-12)

DATASHEET

1.2

Internal Block Overview

This section provides an overview of each of these functional blocks as shown in Figure 1.2, "Internal

Block Diagram".

Figure 1.2 Internal Block Diagram

1.3

10/100 Ethernet PHY

The LAN9211 integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY

can be configured for either 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T) Ethernet operation in

either full or half duplex configurations. The PHY block supports HP Auto-MDIX and auto-negotiation.

Minimal external components are required for the utilization of the Integrated PHY.

1.4

10/100 Ethernet MAC

The transmit and receive data paths are separate within the MAC allowing the highest performance

especially in full duplex mode. The data paths connect to the PIO interface Function via separate

busses to increase performance. Payload data as well as transmit and receive status is passed on

these busses.

A third internal bus is used to access the MAC’s Control and Status Registers (CSR’s). This bus is

accessible from the host through the PIO interface function.

On the backend, the MAC interfaces with the internal 10/100 PHY through a MII (Media Independent

Interface) port internal to the LAN9211. The MAC CSR's also provide a mechanism for accessing the

PHY’s internal registers through the internal SMI (Serial Management Interface) bus.

The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and a 128 Byte receive

FIFO which is separate from the TX and RX FIFOs. The FIFOs within the MAC are not directly

accessible from the host interface. The differentiation between the TX/RX FIFO memory buffers and

the MAC buffers is that when the transmit or receive packets are in the MAC buffers, the host no longer

10/100

Ethernet

PHY

10/100

Ethernet

MAC

2kB to 14kB

Configurable TX FIFO

2kB to 14kB

Configurable RX FIFO

Interrupt

Controller

GP Timer

PIO Controller

3.3V to 1.8V

Core Regulator

PLL

25MHz

+3.3V

EEPROM

Controller

EEPROM

(Optional)

RX Status FIFO

TX Status FIFO

MIL - TX Elastic

Buffer - 2K bytes

MIL - RX Elastic

Buffer - 128 bytes

Power

Management

IRQ

FIFO_SEL

PME

Wakup Indicator

Host Bus Interface

(HBI)

16-bit SRAM I/F

RX Checksum

Offload Engine

TX Checksum

Offload Engine

LAN

LAN9211 数据表(PDF) 11 Page - SMSC Corporation

LAN9211 数据表(HTML) 11 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载