LAN9211 datasheet(77/147 Pages) SMSC

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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

SMSC LAN9211

Revision 2.9 (03-01-12)

DATASHEET

5.1

5.2

RX and TX FIFO Ports

The LAN9211 contains four host-accessible FIFOs: RX Status, RX Data, TX Status, and TX Data

FIFOs. The sizes Data FIFOs and the RX Status FIFO are configurable through the CSRs.

5.2.1

RX FIFO Ports

The RX Data Path contains two Read-Only FIFOs: RX Status and RX Data. The RX Status FIFO has

two ports at different address locations. The RX Status FIFO Port causes the top of the RX Status

FIFO to be “popped”, and is destructive. The RX Status FIFO PEEK Port allows the top of the RX

Status FIFO to be read without “popping” it.

The RX Data FIFO has a single port; reading data from this port always causes the top of the RX Data

FIFO to be “popped”. This port is aliased to 16 WORD locations. The host may access the top of the

RX Data FIFO through any of these locations.

5.2.2

TX FIFO Ports

The TX Data Path consists of two FIFOs, TX Status and RX Data. The TX Status FIFO also has two

ports at different locations. When the TX Status FIFO Port is read, the top of the TX Status FIFO is

popped. When the TX Status FIFO PEEK Port is read, the top of the TX Status FIFO is not popped.

The TX data FIFO is Write Only. It is aliased to 16 WORD locations . The host may access the top of

the TX Data FIFO through any of these locations.

SYMBOL

DESCRIPTION

Read Only: If a register is read only, writes to this register have no effect.

Write Only: If a register is write only, reads always return 0.

R/W

Read/Write: A register with this attribute can be read and written

R/WC

Read/Write Clear: A register bit with this attribute can be read and written. However, a write of a 1

clears (sets to 0) the corresponding bit and a write of a 0 has no effect.

Read to Clear: A register bit with this attribute is cleared when read.

Latch Low: Clear on read of register

Latch High: Clear on read of register

Self-Clearing

NASR

Not Affected by Software Reset

Reserved

Bits

Certain bits within registers are listed as “Reserved”. Unless stated otherwise, these bits must be

written with zeros for future compatibility. The values of these bits are not guaranteed when read.

Reserved

Registers

Certain configuration registers within the LAN9211 are listed as “Reserved”. These registers are not

guaranteed to return any particular value when read. These registers must not be written to or

modified by system failure; doing so could result in failure of the device and system.

Default

States

At Reset - System reset or Software Reset - internal registers are set to their default states.

The default states provide a minimum level of functionality needed to successfully bring up a system,

but do not necessarily provide desired or optimal configuration of the device. It is the responsibility

of the system initialization software to properly determine the operating parameters and optional

system features that are applicable, and to program the LAN9211 registers accordingly.

LAN9211 数据表(PDF) 77 Page - SMSC Corporation

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