LAN9211 datasheet(46/147 Pages) SMSC

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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

Revision 2.9 (03-01-12)

SMSC LAN9211

DATASHEET

3.10.3.2

Energy Detect Power-Down

This power-down mode is activated by setting the Phy register bit 17.13 to 1. Please refer to Section

5.5.8, "Mode Control/Status," on page 121 for additional information on this register. In this mode when

no energy is present on the line, the PHY is powered down, with the exception of the management

interface, the SQUELCH circuit and the ENERGYON logic. The ENERGYON logic is used to detect

the presence of valid energy from 100Base-TX, 10Base-T, or Auto-negotiation signals

In this mode, when the ENERGYON signal is low, the PHY is powered-down, and nothing is

transmitted. When energy is received - link pulses or packets - the ENERGYON signal goes high, and

the PHY powers-up. It automatically resets itself into the state it had prior to power-down, and asserts

the INT7.1 bit of the register defined in Section 5.5.11, "Interrupt Source Flag," on page 124. If the

ENERGYON interrupt is enabled, this event will cause an interrupt to the host. The first and possibly

the second packet to activate ENERGYON may be lost. When 17.13 is low, energy detect power-down

is disabled.

3.11

Detailed Reset Description

The LAN9211 has four reset sources:

Hardware Reset Input Pin (nRESET)

Soft Reset (SRST)

PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)

PHY Soft Reset via PHY Basic Control Register (PHY REG 0.15)

Table 3.11 shows the effect of the various reset sources on the LAN9211's circuitry.

Note: For proper operation, the LAN9211 must be reset on power-up via the hardware reset input

(nRESET) or soft reset (SRST). To accomplish this, nRESET should be asserted for the

minimum period of 30ms at power-up. Alternatively, a soft reset may be performed following

power-up by setting the SRST bit of the HW_CFG register once the READY bit in the

PMT_CTRL register has been set. Refer to Section 3.11.1, "Hardware Reset Input (nRESET)"

and Section 3.11.3, "Soft Reset (SRST)" for additional information.

Note 3.11 After any PHY reset, the application must wait until the “Link Status” bit in the PHY’s “Basic

Status Register” (PHY Reg. 1.2) is set before attempting to transmit or receive data.

Note 3.12 After a power-up, nRESET or SRST, the LAN9211 will automatically check for the

presence of an external EEPROM. After any of these resets the application must verify

that the EPC Busy Bit (E2P_CMD, bit 31) is cleared before attempting to access the

EEPROM, or change the function of the GPO/GPIO signals, or before modifying the

ADDRH or ADDRL registers in the MAC.

Note 3.13 HBI - “Host Bus Interface”, NASR - Not affected by software reset.

Table 3.11 Reset Sources and Affected Circuitry

RESET

SOURCE

PLL

HBI

Note

3.13

NASR

REGISTERS

Note 3.13

MIL

MAC

PHY

Note 3.11

EEPROM MAC

ADDR.

RELOAD

Note 3.12

CONFIG.

STRAPS

LATCHED

nRESET

SRST

PHY_RST

PHY REG 0.15

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