LAN9211 datasheet(81/147 Pages) SMSC

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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

SMSC LAN9211

Revision 2.9 (03-01-12)

DATASHEET

5.3.3

INT_STS—Interrupt Status Register

This register contains the current status of the generated interrupts. Writing a 1 to the corresponding

bits acknowledges and clears the interrupt.

Offset:

58h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

Software Interrupt (SW_INT). This interrupt is generated when the

SW_INT_EN bit is set high. Writing a one clears this interrupt.

R/WC

30-26

Reserved

TX Stopped (TXSTOP_INT). This interrupt is issued when STOP_TX bit

in TX_CFG is set, and the transmitter is halted.

R/WC

RX Stopped (RXSTOP_INT). This interrupt is issued when the receiver is

halted.

R/WC

RX Dropped Frame Counter Halfway (RXDFH_INT). This interrupt is

issued when the RX Dropped Frames Counter counts past its halfway

point (7FFFFFFFh to 80000000h).

R/WC

Reserved

TX IOC Interrupt (TX_IOC). When a buffer with the IOC flag set has

finished being loaded into the TX FIFO, this interrupt is generated.

R/WC

RX DMA Interrupt (RXD_INT). This interrupt is issued when the amount

of data programmed in the RX DMA Count (RX_DMA_CNT) field of the

RX_CFG register has been transferred out of the RX FIFO.

R/WC

GP Timer (GPT_INT). This interrupt is issued when the General Purpose

timer wraps past zero to FFFFh.

R/WC

PHY (PHY_INT). Indicates a PHY Interrupt event.

Power Management Event Interrupt (PME_INT). This interrupt is issued

when a Power Management Event is detected as configured in the

PMT_CTRL register. This interrupt functions independent of the PME

signal, and will still function if the PME signal is disabled. Writing a '1'

clears this bit regardless of the state of the PME hardware signal.

Notes:

Detection of a Power Management Event, and assertion of the PME

signal will not wakeup the LAN9211. The LAN9211 will only wake up

when it detects a host write cycle of any data to the BYTE_TEST

The Interrupt Deassertion interval does not apply to the PME interrupt.

R/WC

TX Status FIFO Overflow (TXSO). Generated when the TX Status

FIFO overflows.

R/WC

Receive Watchdog Time-out (RWT). Interrupt is generated when a

packet larger than 2048 bytes has been received.

R/WC

Receiver Error (RXE). Indicates that the receiver has encountered an

error. Please refer to Section 3.13.5, "Receiver Errors," on page 65 for a

description of the conditions that will cause an RXE.

R/WC

Transmitter Error (TXE). When generated, indicates that the

transmitter has encountered an error. Please refer to Section 3.12.7,

"Transmitter Errors," on page 60, for a description of the conditions that

will cause a TXE.

R/WC

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