LAN9211 datasheet(42/147 Pages) SMSC

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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

Revision 2.9 (03-01-12)

SMSC LAN9211

DATASHEET

Table 3.9, "Required EECLK Cycles", shown below, shows the number of EECLK cycles required for

each EEPROM operation.

3.9.2.2

MAC Address Reload

The MAC address can be reloaded from the EEPROM via a host command to the E2P_CMD register.

If a value of 0xA5h is not found in the first address of the EEPROM, the EEPROM is assumed to be

un-programmed and MAC Address Reload operation will fail. The “MAC Address Loaded” bit indicates

a successful load of the MAC address. The EPC_LOAD bit is set after a successful reload of the MAC

address.

3.9.2.3

EEPROM Command and Data Registers

Refer to Section 5.3.23, "E2P_CMD – EEPROM Command Register," on page 101 and Section 5.3.24,

"E2P_DATA – EEPROM Data Register," on page 103 for a detailed description of these registers.

Supported EEPROM operations are described in these sections.

3.9.2.4

EEPROM Timing

Refer to Section 6.9, "EEPROM Timing," on page 136 for detailed EEPROM timing specifications.

3.10

Power Management

The LAN9211 supports power-down modes to allow applications to minimize power consumption. The

following sections describe these modes.

3.10.1

System Description

Power is reduced to various modules by disabling the clocks as outlined in Table 3.10, “Power

Management States,” on page 44. All configuration data is saved when in either of the two low power

states. Register contents are not affected unless specifically indicated in the register description.

3.10.2

Functional Description

There is one normal operating power state, D0 and there are two power saving states: D1, and D2.

Upon entry into either of the two power saving states, only the PMT_CTRL register is accessible for

read operations. In either of the power saving states the READY bit in the PMT_CTRL register will be

cleared. Reads of any other addresses are forbidden until the READY bit is set. All writes, with the

exception of the wakeup write to BYTE_TEST, are also forbidden until the READY bit is set. Only when

in the D0 (Normal) state, when the READY bit is set, can the rest of the device be accessed.

Table 3.9 Required EECLK Cycles

OPERATION

REQUIRED EECLK CYCLES

ERASE

ERAL

EWDS

EWEN

READ

WRITE

WRAL

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