LAN9211 datasheet(21/147 Pages) SMSC

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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

SMSC LAN9211

Revision 2.9 (03-01-12)

DATASHEET

Chapter 3 Functional Description

3.1

10/100 Ethernet MAC

The Ethernet Media Access controller (MAC) incorporates the essential protocol requirements for

operating an Ethernet/IEEE 802.3-compliant node and provides an interface between the host

subsystem and the internal Ethernet PHY. The MAC can operate in either 100-Mbps or 10-Mbps mode.

The MAC operates in both half-duplex and full-duplex modes. When operating in half-duplex mode,

the MAC complies fully with Section 4 of ISO/IEC 8802-3 (ANSI/IEEE standard) and ANSI/IEEE 802.3

standards. When operating in full-duplex mode, the MAC complies with IEEE 802.3x full-duplex

operation standard.

The MAC provides programmable enhanced features designed to minimize host supervision, bus

utilization, and pre- or post-message processing. These features include the ability to disable retries

after a collision, dynamic FCS (Frame Check Sequence) generation on a frame-by-frame basis,

automatic pad field insertion and deletion to enforce minimum frame size attributes, layer 3 checksum

calculation for transmit and receive operations, and automatic retransmission and detection of collision

frames.

The MAC can sustain transmission or reception of minimally-sized back-to-back packets at full line

speed with an interpacket gap (IPG) of 9.6 microseconds for 10 Mbps and 0.96 microseconds for 100

Mbps.

The primary attributes of the MAC Function are:

Transmit and receive message data encapsulation

Framing (frame boundary delimitation, frame synchronization)

Error detection (physical medium transmission errors)

Media access management

Medium allocation (collision detection, except in full-duplex operation)

Contention resolution (collision handling, except in full-duplex operation)

Flow control during full-duplex mode

Decoding of control frames (PAUSE command) and disabling the transmitter

Generation of control frames

Interface to the internal PHY.

Checksum offload engine for calculation of layer 3 transmit and receive checksum.

The transmit and receive data paths are separate within the LAN9211 from the MAC to host interface

allowing the highest performance, especially in full duplex mode. Payload data as well as transmit and

receive status are passed on these busses.

A third internal bus is used to access the MAC’s “Control and Status Registers” (CSR’s). This bus is

also accessible from the host.

On the backend, the MAC interfaces with the 10/100 PHY through an MII (Media Independent

Interface) port which is internal to the LAN9211. The MAC CSR's also provide a mechanism for

accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus.

The receive and transmit FIFOs allow increased packet buffer storage to the MAC. The FIFOs are a

conduit between the host interface and the MAC through which all transmitted and received data and

status information is passed. Deep FIFOs allow a high degree of latency tolerance relative to the

various transport and OS software stacks reducing and minimizing overrun conditions. Like the MAC,

the FIFOs have separate receive and transmit data paths.

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